#define AT91_GPIO_CHIP(name, base_gpio, nr_gpio) \ { \ .chip = { \ .label = name, \ .direction_input = at91_gpiolib_direction_input, \ .direction_output = at91_gpiolib_direction_output, \ .get = at91_gpiolib_get, \ .set = at91_gpiolib_set, \ .dbg_show = at91_gpiolib_dbg_show, \ .base = base_gpio, \ .ngpio = nr_gpio, \ }, \ } static struct at91_gpio_chip gpio_chip[] = { AT91_GPIO_CHIP("A", 0x00 + PIN_BASE, 32), AT91_GPIO_CHIP("B", 0x20 + PIN_BASE, 32), AT91_GPIO_CHIP("C", 0x40 + PIN_BASE, 32), AT91_GPIO_CHIP("D", 0x60 + PIN_BASE, 32), AT91_GPIO_CHIP("E", 0x80 + PIN_BASE, 32), }; static int gpio_banks; static inline void __iomem *pin_to_controller(unsigned pin) { pin -= PIN_BASE; pin /= 32; if (likely(pin < gpio_banks)) return gpio_chip[pin].regbase;
{ \ .chip = { \ .label = name, \ .request = at91_gpiolib_request, \ .direction_input = at91_gpiolib_direction_input, \ .direction_output = at91_gpiolib_direction_output, \ .get = at91_gpiolib_get, \ .set = at91_gpiolib_set, \ .dbg_show = at91_gpiolib_dbg_show, \ .to_irq = at91_gpiolib_to_irq, \ .ngpio = MAX_NB_GPIO_PER_BANK, \ }, \ } static struct at91_gpio_chip gpio_chip[] = { AT91_GPIO_CHIP("pioA"), AT91_GPIO_CHIP("pioB"), AT91_GPIO_CHIP("pioC"), AT91_GPIO_CHIP("pioD"), AT91_GPIO_CHIP("pioE"), }; static int gpio_banks; static unsigned long at91_gpio_caps; /* All PIO controllers support PIO3 features */ #define AT91_GPIO_CAP_PIO3 (1 << 0) #define has_pio3() (at91_gpio_caps & AT91_GPIO_CAP_PIO3) /*--------------------------------------------------------------------------*/