Esempio n. 1
0
static void __init eco920_board_init(void)
{
	/* DBGU on ttyS0. (Rx & Tx only */
	at91_register_uart(0, 0, 0);
	at91_add_device_serial();
	at91_add_device_eth(&eco920_eth_data);
	at91_add_device_usbh(&eco920_usbh_data);
	at91_add_device_udc(&eco920_udc_data);

	at91_add_device_mci(0, &eco920_mci0_data);
	platform_device_register(&eco920_flash);

	at91_ramc_write(0, AT91_SMC_CSR(7),	AT91_SMC_RWHOLD_(1)
				| AT91_SMC_RWSETUP_(1)
				| AT91_SMC_DBW_8
				| AT91_SMC_WSEN
				| AT91_SMC_NWS_(15));

	at91_set_A_periph(AT91_PIN_PC6, 1);

	at91_set_gpio_input(AT91_PIN_PA23, 0);
	at91_set_deglitch(AT91_PIN_PA23, 1);

/* Initialization of the Static Memory Controller for Chip Select 3 */
	at91_ramc_write(0, AT91_SMC_CSR(3),
		AT91_SMC_DBW_16  |	/* 16 bit */
		AT91_SMC_WSEN    |
		AT91_SMC_NWS_(5) |	/* wait states */
		AT91_SMC_TDF_(1)	/* float time */
	);

	at91_add_device_spi(eco920_spi_devices, ARRAY_SIZE(eco920_spi_devices));
	/* LEDs */
	at91_gpio_leds(eco920_leds, ARRAY_SIZE(eco920_leds));
}
Esempio n. 2
0
static void yl9200_init_video(void)
{
	/* NWAIT Signal */
	at91_set_A_periph(AT91_PIN_PC6, 0);

	/* Initialization of the Static Memory Controller for Chip Select 2 */
	at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16		/* 16 bit */
			| AT91_SMC_WSEN | AT91_SMC_NWS_(0x4)	/* wait states */
			| AT91_SMC_TDF_(0x100)			/* float time */
	);
}
void __init at91_add_device_cf(struct at91_cf_data *data)
{
	unsigned int csa;

	if (!data)
		return;

	data->chipselect = 4;		/* can only use EBI ChipSelect 4 */

	/* CF takes over CS4, CS5, CS6 */
	csa = at91_ramc_read(0, AT91_EBI_CSA);
	at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);

	/*
	 * Static memory controller timing adjustments.
	 * REVISIT:  these timings are in terms of MCK cycles, so
	 * when MCK changes (cpufreq etc) so must these values...
	 */
	at91_ramc_write(0, AT91_SMC_CSR(4),
				  AT91_SMC_ACSS_STD
				| AT91_SMC_DBW_16
				| AT91_SMC_BAT
				| AT91_SMC_WSEN
				| AT91_SMC_NWS_(32)	/* wait states */
				| AT91_SMC_RWSETUP_(6)	/* setup time */
				| AT91_SMC_RWHOLD_(4)	/* hold time */
	);

	/* input/irq */
	if (gpio_is_valid(data->irq_pin)) {
		at91_set_gpio_input(data->irq_pin, 1);
		at91_set_deglitch(data->irq_pin, 1);
	}
	at91_set_gpio_input(data->det_pin, 1);
	at91_set_deglitch(data->det_pin, 1);

	/* outputs, initially off */
	if (gpio_is_valid(data->vcc_pin))
		at91_set_gpio_output(data->vcc_pin, 0);
	at91_set_gpio_output(data->rst_pin, 0);

	/* force poweron defaults for these pins ... */
	at91_set_A_periph(AT91_PIN_PC9, 0);	/* A25/CFRNW */
	at91_set_A_periph(AT91_PIN_PC10, 0);	/* NCS4/CFCS */
	at91_set_A_periph(AT91_PIN_PC11, 0);	/* NCS5/CFCE1 */
	at91_set_A_periph(AT91_PIN_PC12, 0);	/* NCS6/CFCE2 */

	/* nWAIT is _not_ a default setting */
	at91_set_A_periph(AT91_PIN_PC6, 1);	/* nWAIT */

	cf_data = *data;
	platform_device_register(&at91rm9200_cf_device);
}
Esempio n. 4
0
static void __init ek_init_video(void)
{
	/* NWAIT Signal */
	at91_set_A_periph(AT91_PIN_PC6, 0);

	/* Initialization of the Static Memory Controller for Chip Select 3 */
	at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_DBW_16			/* 16 bit */
				| AT91_SMC_WSEN | AT91_SMC_NWS_(5)	/* wait states */
				| AT91_SMC_TDF_(1)			/* float time */
	);

	at91_ics1523_init();
}
static void __init yl_9200_init_video(void)
{
	at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6);
	at91_sys_write(AT91_PIOC + PIO_BSR,0);
	at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6);

	at91_sys_write( AT91_SMC_CSR(2),
	AT91_SMC_NWS_(0x4) |
	AT91_SMC_WSEN |
	AT91_SMC_TDF_(0x100) |
	AT91_SMC_DBW
	);



}
Esempio n. 6
0
/*
 * Enable NAND and detect card.
 */
static void at91_nand_enable(struct at91_nand_host *host)
{
	unsigned int csa;

	/* Setup Smart Media, first enable the address range of CS3 */
	csa = at91_sys_read(AT91_EBI_CSA);
	at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);

	/* set the bus interface characteristics */
	at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
				| AT91_SMC_NWS_(5)
				| AT91_SMC_TDF_(1)
				| AT91_SMC_RWSETUP_(0)	/* tDS Data Set up Time 30 - ns */
				| AT91_SMC_RWHOLD_(1)	/* tDH Data Hold Time 20 - ns */
	);

	if (host->board->enable_pin)
		at91_set_gpio_value(host->board->enable_pin, 0);
}
void __init at91_add_device_nand(struct atmel_nand_data *data)
{
	unsigned int csa;

	if (!data)
		return;

	/* enable the address range of CS3 */
	csa = at91_ramc_read(0, AT91_EBI_CSA);
	at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);

	/* set the bus interface characteristics */
	at91_ramc_write(0, AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
		| AT91_SMC_NWS_(5)
		| AT91_SMC_TDF_(1)
		| AT91_SMC_RWSETUP_(0)	/* tDS Data Set up Time 30 - ns */
		| AT91_SMC_RWHOLD_(1)	/* tDH Data Hold Time 20 - ns */
	);

	/* enable pin */
	if (gpio_is_valid(data->enable_pin))
		at91_set_gpio_output(data->enable_pin, 1);

	/* ready/busy pin */
	if (gpio_is_valid(data->rdy_pin))
		at91_set_gpio_input(data->rdy_pin, 1);

	/* card detect pin */
	if (gpio_is_valid(data->det_pin))
		at91_set_gpio_input(data->det_pin, 1);

	at91_set_A_periph(AT91_PIN_PC1, 0);		/* SMOE */
	at91_set_A_periph(AT91_PIN_PC3, 0);		/* SMWE */

	nand_data = *data;
	platform_device_register(&at91rm9200_nand_device);
}
void __init at91_add_device_nand(struct atmel_nand_data *data)
{
	unsigned int csa;

	if (!data)
		return;

	/* enable the address range of CS3 */
	csa = at91_sys_read(AT91_EBI_CSA);
	at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);

	/* set the bus interface characteristics */
	at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
		| AT91_SMC_NWS_(5)
		| AT91_SMC_TDF_(1)
		| AT91_SMC_RWSETUP_(0)	/* tDS Data Set up Time 30 - ns */
		| AT91_SMC_RWHOLD_(1)	/* tDH Data Hold Time 20 - ns */
	);

	/* enable pin */
	if (data->enable_pin)
		at91_set_gpio_output(data->enable_pin, 1);

	/* ready/busy pin */
	if (data->rdy_pin)
		at91_set_gpio_input(data->rdy_pin, 1);

	/* card detect pin */
	if (data->det_pin)
		at91_set_gpio_input(data->det_pin, 1);

	at91_set_A_periph(AT91_PIN_PC1, 0);		/* SMOE */
	at91_set_A_periph(AT91_PIN_PC3, 0);		/* SMWE */

	add_generic_device("atmel_nand", 0, NULL, AT91_CHIPSELECT_3, 0x10,
			   IORESOURCE_MEM, data);
}
Esempio n. 9
0
static int __init at91_cf_probe(struct device *dev)
{
	struct at91_cf_socket	*cf;
	struct at91_cf_data	*board = dev->platform_data;
	struct platform_device	*pdev = to_platform_device(dev);
	struct resource		*io;
	unsigned int		csa;
	int			status;

	if (!board || !board->det_pin || !board->rst_pin)
		return -ENODEV;

	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!io)
		return -ENODEV;

	cf = kcalloc(1, sizeof *cf, GFP_KERNEL);
	if (!cf)
		return -ENOMEM;

	cf->board = board;
	cf->pdev = pdev;
	dev_set_drvdata(dev, cf);

	/* CF takes over CS4, CS5, CS6 */
	csa = at91_sys_read(AT91_EBI_CSA);
	at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);

	/* force poweron defaults for these pins ... */
	(void) at91_set_A_periph(AT91_PIN_PC9, 0);	/* A25/CFRNW */
	(void) at91_set_A_periph(AT91_PIN_PC10, 0);	/* NCS4/CFCS */
	(void) at91_set_A_periph(AT91_PIN_PC11, 0);	/* NCS5/CFCE1 */
	(void) at91_set_A_periph(AT91_PIN_PC12, 0);	/* NCS6/CFCE2 */

	/* nWAIT is _not_ a default setting */
	(void) at91_set_A_periph(AT91_PIN_PC6, 1);	/*  nWAIT */

	/*
	 * Static memory controller timing adjustments.
	 * REVISIT:  these timings are in terms of MCK cycles, so
	 * when MCK changes (cpufreq etc) so must these values...
	 */
	at91_sys_write(AT91_SMC_CSR(4),
				  AT91_SMC_ACSS_STD
				| AT91_SMC_DBW_16
				| AT91_SMC_BAT
				| AT91_SMC_WSEN
				| AT91_SMC_NWS_(32)	/* wait states */
				| AT91_SMC_RWSETUP_(6)	/* setup time */
				| AT91_SMC_RWHOLD_(4)	/* hold time */
	);

	/* must be a GPIO; ergo must trigger on both edges */
	status = request_irq(board->det_pin, at91_cf_irq,
			SA_SAMPLE_RANDOM, driver_name, cf);
	if (status < 0)
		goto fail0;

	/*
	 * The card driver will request this irq later as needed.
	 * but it causes lots of "irqNN: nobody cared" messages
	 * unless we report that we handle everything (sigh).
	 * (Note:  DK board doesn't wire the IRQ pin...)
	 */
	if (board->irq_pin) {
		status = request_irq(board->irq_pin, at91_cf_irq,
				SA_SHIRQ, driver_name, cf);
		if (status < 0)
			goto fail0a;
		cf->socket.pci_irq = board->irq_pin;
	} else
		cf->socket.pci_irq = NR_IRQS + 1;

	/* pcmcia layer only remaps "real" memory not iospace */
	cf->socket.io_offset = (unsigned long) ioremap(CF_IO_PHYS, SZ_2K);
	if (!cf->socket.io_offset)
		goto fail1;

	/* reserve CS4, CS5, and CS6 regions; but use just CS4 */
	if (!request_mem_region(io->start, io->end + 1 - io->start,
				driver_name))
		goto fail1;

	pr_info("%s: irqs det #%d, io #%d\n", driver_name,
		board->det_pin, board->irq_pin);

	cf->socket.owner = THIS_MODULE;
	cf->socket.dev.dev = dev;
	cf->socket.ops = &at91_cf_ops;
	cf->socket.resource_ops = &pccard_static_ops;
	cf->socket.features = SS_CAP_PCCARD | SS_CAP_STATIC_MAP
				| SS_CAP_MEM_ALIGN;
	cf->socket.map_size = SZ_2K;
	cf->socket.io[0].res = io;

	status = pcmcia_register_socket(&cf->socket);
	if (status < 0)
		goto fail2;

	return 0;

fail2:
	iounmap((void __iomem *) cf->socket.io_offset);
	release_mem_region(io->start, io->end + 1 - io->start);
fail1:
	if (board->irq_pin)
		free_irq(board->irq_pin, cf);
fail0a:
	free_irq(board->det_pin, cf);
fail0:
	at91_sys_write(AT91_EBI_CSA, csa);
	kfree(cf);
	return status;
}