/**
Initialize the state information for the CPU Architectural Protocol
@param ImageHandle of the loaded driver
@param SystemTable Pointer to the System Table
@retval EFI_SUCCESS Protocol registered
@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
@retval EFI_DEVICE_ERROR Hardware problems
**/
EFI_STATUS
GicV2DxeInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
UINTN Index;
UINT32 RegOffset;
UINTN RegShift;
UINT32 CpuTarget;
// Make sure the Interrupt Controller Protocol is not already installed in the system.
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
mGicInterruptInterfaceBase = PcdGet32 (PcdGicInterruptInterfaceBase);
mGicDistributorBase = PcdGet32 (PcdGicDistributorBase);
mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);
for (Index = 0; Index < mGicNumInterrupts; Index++) {
GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);
// Set Priority
RegOffset = Index / 4;
RegShift = (Index % 4) * 8;
MmioAndThenOr32 (
mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
~(0xff << RegShift),
ARM_GIC_DEFAULT_PRIORITY << RegShift
);
}
//
// Targets the interrupts to the Primary Cpu
//
// Only Primary CPU will run this code. We can identify our GIC CPU ID by reading
// the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each
// connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31.
// More Info in the GIC Specification about "Interrupt Processor Targets Registers"
//
// Read the first Interrupt Processor Targets Register (that corresponds to the 4
// first SGIs)
CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR);
// The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value
// is 0 when we run on a uniprocessor platform.
if (CpuTarget != 0) {
// The 8 first Interrupt Processor Targets Registers are read-only
for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);
}
}
// Set binary point reg to 0x7 (no preemption)
MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCBPR, 0x7);
// Set priority mask reg to 0xff to allow all priorities through
MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0xff);
// Enable gic cpu interface
ArmGicEnableInterruptInterface (mGicInterruptInterfaceBase);
// Enable gic distributor
ArmGicEnableDistributor (mGicDistributorBase);
Status = InstallAndRegisterInterruptService (
&gHardwareInterruptV2Protocol, GicV2IrqInterruptHandler, GicV2ExitBootServicesEvent);
return Status;
}
VOID
CEntryPoint (
IN UINTN MpId,
IN UINTN SecBootMode
)
{
CHAR8 Buffer[100];
UINTN CharCount;
UINTN JumpAddress;
// Invalidate the data cache. Doesn't have to do the Data cache clean.
ArmInvalidateDataCache ();
// Invalidate Instruction Cache
ArmInvalidateInstructionCache ();
// Invalidate I & D TLBs
ArmInvalidateInstructionAndDataTlb ();
// CPU specific settings
ArmCpuSetup (MpId);
// Enable Floating Point Coprocessor if supported by the platform
if (FixedPcdGet32 (PcdVFPEnabled)) {
ArmEnableVFP ();
}
// Initialize peripherals that must be done at the early stage
// Example: Some L2 controller, interconnect, clock, DMC, etc
ArmPlatformSecInitialize (MpId);
// Primary CPU clears out the SCU tag RAMs, secondaries wait
if (ArmPlatformIsPrimaryCore (MpId) && (SecBootMode == ARM_SEC_COLD_BOOT)) {
if (ArmIsMpCore()) {
// Signal for the initial memory is configured (event: BOOT_MEM_INIT)
ArmCallSEV ();
}
// SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
// In non SEC modules the init call is in autogenerated code.
SerialPortInitialize ();
// Start talking
if (FixedPcdGetBool (PcdTrustzoneSupport)) {
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Secure firmware (version %s built at %a on %a)\n\r",
(CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
} else {
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Boot firmware (version %s built at %a on %a)\n\r",
(CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
}
SerialPortWrite ((UINT8 *) Buffer, CharCount);
// Initialize the Debug Agent for Source Level Debugging
InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);
SaveAndSetDebugTimerInterrupt (TRUE);
// Enable the GIC distributor and CPU Interface
// - no other Interrupts are enabled, doesn't have to worry about the priority.
// - all the cores are in secure state, use secure SGI's
ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
} else {
// Enable the GIC CPU Interface
ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
}
// Enable Full Access to CoProcessors
ArmWriteCpacr (CPACR_CP_FULL_ACCESS);
// Test if Trustzone is supported on this platform
if (FixedPcdGetBool (PcdTrustzoneSupport)) {
if (ArmIsMpCore ()) {
// Setup SMP in Non Secure world
ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId));
}
// Either we use the Secure Stacks for Secure Monitor (in this case (Base == 0) && (Size == 0))
// Or we use separate Secure Monitor stacks (but (Base != 0) && (Size != 0))
ASSERT (((PcdGet32(PcdCPUCoresSecMonStackBase) == 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) == 0)) ||
((PcdGet32(PcdCPUCoresSecMonStackBase) != 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) != 0)));
// Enter Monitor Mode
enter_monitor_mode (
(UINTN)TrustedWorldInitialization, MpId, SecBootMode,
(VOID*) (PcdGet32 (PcdCPUCoresSecMonStackBase) +
(PcdGet32 (PcdCPUCoreSecMonStackSize) * (ArmPlatformGetCorePosition (MpId) + 1)))
);
} else {
if (ArmPlatformIsPrimaryCore (MpId)) {
SerialPrint ("Trust Zone Configuration is disabled\n\r");
}
// With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
// If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
// Status Register as the the current one (CPSR).
copy_cpsr_into_spsr ();
// Call the Platform specific function to execute additional actions if required
JumpAddress = PcdGet32 (PcdFvBaseAddress);
ArmPlatformSecExtraAction (MpId, &JumpAddress);
NonTrustedWorldTransition (MpId, JumpAddress);
}
ASSERT (0); // We must never return from the above function
}
