Esempio n. 1
0
static void __init set_pata_read_timings(int bank, int cycle_time,
		int IORD_start, int IORD_end, int RD_latch)
{
	cycle_time = cycle_time / 10;
	IORD_start = IORD_start / 5;
	IORD_end = IORD_end / 5;
	RD_latch = RD_latch / 10;

	writel((cycle_time << 24) | (IORD_start << 8) | (IORD_end << 12),
			emi_control + BANK_EMICONFIGDATA(bank, 1));
	writel(0x791 | (RD_latch << 20),
			emi_control + BANK_EMICONFIGDATA(bank, 0));
}
Esempio n. 2
0
void emi_bank_write_cs_enable(int bank, int enable)
{
    unsigned long reg;

    BUG_ON(bank < 0 || bank >= EMI_BANKS);
    BUG_ON(!emi_initialised);

    reg = readl(emi_control + BANK_EMICONFIGDATA(bank, 0));

    if (enable)
        reg |= EMI_CFG_DATA0_WRITE_CS;
    else
        reg &= ~EMI_CFG_DATA0_WRITE_CS;

    writel(reg, emi_control + BANK_EMICONFIGDATA(bank, 0));
}
Esempio n. 3
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static void set_nand_read_timings(int bank, int cycle_time,
		int IORD_start, int IORD_end,
		int RD_latch, int busreleasetime,
		int wait_active_low )
{
	cycle_time = cycle_time / 10;		/* cycles */
	IORD_start = IORD_start / 5;		/* phases */
	IORD_end = IORD_end / 5;		/* phases */
	RD_latch = RD_latch / 10;		/* cycles */
	busreleasetime = busreleasetime / 10;   /* cycles */

	writel(0x04000699 | (busreleasetime << 11) | (RD_latch << 20) | (wait_active_low << 25),
			emi_control + BANK_EMICONFIGDATA(bank, 0));

	writel((cycle_time << 24) | (IORD_start << 12) | (IORD_end << 8),
			emi_control + BANK_EMICONFIGDATA(bank, 1));
}
Esempio n. 4
0
static int emi_hibernation(int resuming)
{
    int idx;
    int bank, data;
    static struct emi_pm *emi_saved_data;

    if (resuming) {
        if (emi_saved_data) {
            /* restore the previous common value */
            for (idx = 0; idx < emi_num_common_cfg-4; ++idx)
                writel(emi_saved_data->common_cfg[idx],
                       emi_control+EMI_COMMON_CFG(idx));
            writel(emi_saved_data->common_cfg[12], emi_control
                   + EMI_BANK_ENABLE);
            writel(emi_saved_data->common_cfg[13], emi_control
                   + EMI_BANKNUMBER);
            writel(emi_saved_data->common_cfg[14], emiss_config +
                   EMISS_CONFIG);
            writel(emi_saved_data->common_cfg[15], emiss_config +
                   EMISS_ARBITER_CONFIG);
            /* restore the previous bank values */
            for (bank = 0; bank < emi_num_bank; ++bank) {
                writel(emi_saved_data->bank[bank].base_address,
                       emi_control + BANK_BASEADDRESS(bank));
                for (data = 0; data < emi_num_bank_cfg; ++data)
                    emi_bank_configure(bank, emi_saved_data->bank[bank].cfg);
            }
            kfree(emi_saved_data);
            emi_saved_data = NULL;
        }
        return 0;
    }
    emi_saved_data = kmalloc(sizeof(struct emi_pm), GFP_NOWAIT);
    if (!emi_saved_data) {
        printk(KERN_ERR "Unable to freeze the emi registers\n");
        return -ENOMEM;
    }
    /* save the emi common values */
    for (idx = 0; idx < emi_num_common_cfg-4; ++idx)
        emi_saved_data->common_cfg[idx] =
            readl(emi_control + EMI_COMMON_CFG(idx));
    emi_saved_data->common_cfg[12] = readl(emi_control + EMI_BANK_ENABLE);
    emi_saved_data->common_cfg[13] = readl(emi_control + EMI_BANKNUMBER);
    emi_saved_data->common_cfg[14] = readl(emiss_config + EMISS_CONFIG);
    emi_saved_data->common_cfg[15] =
        readl(emiss_config + EMISS_ARBITER_CONFIG);
    /* save the emi bank value */
    for (bank  = 0; bank < emi_num_bank; ++bank) {
        emi_saved_data->bank[bank].base_address =
            readl(emi_control + BANK_BASEADDRESS(bank));
        for (data = 0; data < emi_num_bank_cfg; ++data)
            emi_saved_data->bank[bank].cfg[data] =
                readl(emi_control + BANK_EMICONFIGDATA(bank, data));
    }
    return 0;
}
Esempio n. 5
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static void set_nand_write_timings(int bank, int cycle_time,
		int IOWR_start, int IOWR_end)
{
	cycle_time = cycle_time / 10;		/* cycles */
	IOWR_start = IOWR_start / 5;		/* phases */
	IOWR_end   = IOWR_end / 5;		/* phases */

	writel((cycle_time << 24) | (IOWR_start << 12) | (IOWR_end << 8),
			emi_control + BANK_EMICONFIGDATA(bank, 2));
}
Esempio n. 6
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static void __init set_pata_write_timings(int bank, int cycle_time,
		int IOWR_start, int IOWR_end)
{
	cycle_time = cycle_time / 10;
	IOWR_start = IOWR_start / 5;
	IOWR_end = IOWR_end / 5;

	writel((cycle_time << 24) | (IOWR_start << 8) | (IOWR_end << 12),
			emi_control + BANK_EMICONFIGDATA(bank, 2));
}
Esempio n. 7
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void emi_bank_configure(int bank, unsigned long data[4])
{
	int i;

	BUG_ON(bank < 0 || bank >= EMI_BANKS);
	BUG_ON(!emi_initialised);

	for (i = 0; i < 4; i++)
		writel(data[i], emi_control + BANK_EMICONFIGDATA(bank, i));
}