struct clk *clk_get(struct device *dev, const char *id) { if (!strcmp(id, "enet0")) return &clk_enet0; if (!strcmp(id, "enet1")) return &clk_enet1; if (!strcmp(id, "enetsw")) return &clk_enetsw; if (!strcmp(id, "ephy")) return &clk_ephy; if (!strcmp(id, "usbh")) return &clk_usbh; if (!strcmp(id, "usbd")) return &clk_usbd; if (!strcmp(id, "spi")) return &clk_spi; if (!strcmp(id, "hsspi")) return &clk_hsspi; if (!strcmp(id, "xtm")) return &clk_xtm; if (!strcmp(id, "periph")) return &clk_periph; if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm")) return &clk_pcm; if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec")) return &clk_ipsec; if ((BCMCPU_IS_6328() || BCMCPU_IS_6362()) && !strcmp(id, "pcie")) return &clk_pcie; return ERR_PTR(-ENOENT); }
/* * IPsec clock */ static void ipsec_set(struct clk *clk, int enable) { if (BCMCPU_IS_6362()) bcm_hwclock_set(CKCTL_6362_IPSEC_EN, enable); else if (BCMCPU_IS_6368()) bcm_hwclock_set(CKCTL_6368_IPSEC_EN, enable); }
static void pcie_set(struct clk *clk, int enable) { if (BCMCPU_IS_6328()) bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable); else if (BCMCPU_IS_6362()) bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable); }
/* * USB device clock */ static void usbd_set(struct clk *clk, int enable) { if (BCMCPU_IS_6328()) bcm_hwclock_set(CKCTL_6328_USBD_EN, enable); else if (BCMCPU_IS_6362()) bcm_hwclock_set(CKCTL_6362_USBD_EN, enable); else if (BCMCPU_IS_6368()) bcm_hwclock_set(CKCTL_6368_USBD_EN, enable); }
/* * HSSPI clock */ static void hsspi_set(struct clk *clk, int enable) { u32 mask; if (BCMCPU_IS_6328()) mask = CKCTL_6328_HSSPI_EN; else if (BCMCPU_IS_6362()) mask = CKCTL_6362_HSSPI_EN; else return; bcm_hwclock_set(mask, enable); }
int __init bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd) { int ret; if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) return -ENODEV; ret = register_shared(); if (ret) return ret; enetsw_res[0].start = bcm63xx_regset_address(RSET_ENETSW); enetsw_res[0].end = enetsw_res[0].start; enetsw_res[0].end += RSET_ENETSW_SIZE - 1; enetsw_res[1].start = bcm63xx_get_irq_number(IRQ_ENETSW_RXDMA0); enetsw_res[2].start = bcm63xx_get_irq_number(IRQ_ENETSW_TXDMA0); if (!enetsw_res[2].start) enetsw_res[2].start = -1; memcpy(bcm63xx_enetsw_device.dev.platform_data, pd, sizeof(*pd)); if (BCMCPU_IS_6328()) enetsw_pd.num_ports = ENETSW_PORTS_6328; else if (BCMCPU_IS_6362() || BCMCPU_IS_6368()) enetsw_pd.num_ports = ENETSW_PORTS_6368; enetsw_pd.dma_has_sram = true; enetsw_pd.dma_chan_width = ENETDMA_CHAN_WIDTH; enetsw_pd.dma_chan_en_mask = ENETDMAC_CHANCFG_EN_MASK; enetsw_pd.dma_chan_int_mask = ENETDMAC_IR_PKTDONE_MASK; ret = platform_device_register(&bcm63xx_enetsw_device); if (ret) return ret; return 0; }
/* * SPI clock */ static void spi_set(struct clk *clk, int enable) { u32 mask; if (BCMCPU_IS_6338()) mask = CKCTL_6338_SPI_EN; else if (BCMCPU_IS_6348()) mask = CKCTL_6348_SPI_EN; else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) mask = CKCTL_6358_SPI_EN; else if (BCMCPU_IS_6362()) mask = CKCTL_6362_SPI_EN; else /* BCMCPU_IS_6368 */ mask = CKCTL_6368_SPI_EN; bcm_hwclock_set(mask, enable); }
/* * attempt to detect the amount of memory installed */ static unsigned int detect_memory_size(void) { unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; u32 val; if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) return bcm_ddr_readl(DDR_CSEND_REG) << 24; if (BCMCPU_IS_6345()) { val = bcm_sdram_readl(SDRAM_MBASE_REG); return val * 8 * 1024 * 1024; } if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) { val = bcm_sdram_readl(SDRAM_CFG_REG); rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT; cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT; is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0; banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1; }
/* * Ethernet switch clock */ static void enetsw_set(struct clk *clk, int enable) { if (BCMCPU_IS_6328()) bcm_hwclock_set(CKCTL_6328_ROBOSW_EN, enable); else if (BCMCPU_IS_6362()) bcm_hwclock_set(CKCTL_6362_ROBOSW_EN, enable); else if (BCMCPU_IS_6368()) bcm_hwclock_set(CKCTL_6368_ROBOSW_EN | CKCTL_6368_SWPKT_USB_EN | CKCTL_6368_SWPKT_SAR_EN, enable); else return; if (enable) { /* reset switch core afer clock change */ bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 1); msleep(10); bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 0); msleep(10); } }
static int __init register_shared(void) { int ret, chan_count; if (shared_device_registered) return 0; bcm63xx_enetdmac_regs_init(); shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA); shared_res[0].end = shared_res[0].start; if (BCMCPU_IS_6345()) shared_res[0].end += (RSET_6345_ENETDMA_SIZE) - 1; else shared_res[0].end += (RSET_ENETDMA_SIZE) - 1; if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) chan_count = 32; else if (BCMCPU_IS_6345()) chan_count = 8; else chan_count = 16; shared_res[1].start = bcm63xx_regset_address(RSET_ENETDMAC); shared_res[1].end = shared_res[1].start; shared_res[1].end += RSET_ENETDMAC_SIZE(chan_count) - 1; shared_res[2].start = bcm63xx_regset_address(RSET_ENETDMAS); shared_res[2].end = shared_res[2].start; shared_res[2].end += RSET_ENETDMAS_SIZE(chan_count) - 1; ret = platform_device_register(&bcm63xx_enet_shared_device); if (ret) return ret; shared_device_registered = 1; return 0; }
/* * early init callback, read nvram data from flash and checksum it */ void __init board_prom_init(void) { unsigned int i; u8 *boot_addr, *cfe; char cfe_version[32]; char *board_name; u32 val; /* read base address of boot chip select (0) * 6328/6362 do not have MPI but boot from a fixed address */ if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) { val = 0x18000000; } else { val = bcm_mpi_readl(MPI_CSBASE_REG(0)); val &= MPI_CSBASE_BASE_MASK; } boot_addr = (u8 *)KSEG1ADDR(val); /* dump cfe version */ cfe = boot_addr + BCM963XX_CFE_VERSION_OFFSET; if (!memcmp(cfe, "cfe-v", 5)) snprintf(cfe_version, sizeof(cfe_version), "%u.%u.%u-%u.%u", cfe[5], cfe[6], cfe[7], cfe[8], cfe[9]); else strcpy(cfe_version, "unknown"); printk(KERN_INFO PFX "CFE version: %s\n", cfe_version); bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET); board_name = bcm63xx_nvram_get_name(); /* find board by name */ for (i = 0; i < ARRAY_SIZE(bcm963xx_boards); i++) { if (strncmp(board_name, bcm963xx_boards[i]->name, 16)) continue; /* copy, board desc array is marked initdata */ memcpy(&board, bcm963xx_boards[i], sizeof(board)); break; } /* bail out if board is not found, will complain later */ if (!board.name[0]) { char name[17]; memcpy(name, board_name, 16); name[16] = 0; printk(KERN_ERR PFX "unknown bcm963xx board: %s\n", name); return; } /* setup pin multiplexing depending on board enabled device, * this has to be done this early since PCI init is done * inside arch_initcall */ val = 0; #ifdef CONFIG_PCI if (board.has_pci) { bcm63xx_pci_enabled = 1; if (BCMCPU_IS_6348()) val |= GPIO_MODE_6348_G2_PCI; } #endif if (board.has_pccard) { if (BCMCPU_IS_6348()) val |= GPIO_MODE_6348_G1_MII_PCCARD; } if (board.has_enet0 && !board.enet0.use_internal_phy) { if (BCMCPU_IS_6348()) val |= GPIO_MODE_6348_G3_EXT_MII | GPIO_MODE_6348_G0_EXT_MII; } if (board.has_enet1 && !board.enet1.use_internal_phy) { if (BCMCPU_IS_6348()) val |= GPIO_MODE_6348_G3_EXT_MII | GPIO_MODE_6348_G0_EXT_MII; } bcm_gpio_writel(val, GPIO_MODE_REG); }
void __init prom_init(void) { u32 reg, mask; bcm63xx_cpu_init(); /* stop any running watchdog */ bcm_wdt_writel(WDT_STOP_1, WDT_CTL_REG); bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG); /* disable all hardware blocks clock for now */ if (BCMCPU_IS_3368()) mask = CKCTL_3368_ALL_SAFE_EN; else if (BCMCPU_IS_6328()) mask = CKCTL_6328_ALL_SAFE_EN; else if (BCMCPU_IS_6338()) mask = CKCTL_6338_ALL_SAFE_EN; else if (BCMCPU_IS_6345()) mask = CKCTL_6345_ALL_SAFE_EN; else if (BCMCPU_IS_6348()) mask = CKCTL_6348_ALL_SAFE_EN; else if (BCMCPU_IS_6358()) mask = CKCTL_6358_ALL_SAFE_EN; else if (BCMCPU_IS_6362()) mask = CKCTL_6362_ALL_SAFE_EN; else if (BCMCPU_IS_6368()) mask = CKCTL_6368_ALL_SAFE_EN; else mask = 0; reg = bcm_perf_readl(PERF_CKCTL_REG); reg &= ~mask; bcm_perf_writel(reg, PERF_CKCTL_REG); /* register gpiochip */ bcm63xx_gpio_init(); /* do low level board init */ board_prom_init(); /* set up SMP */ if (!register_bmips_smp_ops()) { /* * BCM6328 might not have its second CPU enabled, while BCM3368 * and BCM6358 need special handling for their shared TLB, so * disable SMP for now. */ if (BCMCPU_IS_6328()) { reg = bcm_readl(BCM_6328_OTP_BASE + OTP_USER_BITS_6328_REG(3)); if (reg & OTP_6328_REG3_TP1_DISABLED) bmips_smp_enabled = 0; } else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) { bmips_smp_enabled = 0; } if (!bmips_smp_enabled) return; /* * The bootloader has set up the CPU1 reset vector at * 0xa000_0200. * This conflicts with the special interrupt vector (IV). * The bootloader has also set up CPU1 to respond to the wrong * IPI interrupt. * Here we will start up CPU1 in the background and ask it to * reconfigure itself then go back to sleep. */ memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20); __sync(); set_c0_cause(C_SW0); cpumask_set_cpu(1, &bmips_booted_mask); /* * FIXME: we really should have some sort of hazard barrier here */ } }