/* setup the CPU card internal signals */
static const uint32_t tx28_pad_setup[] = {
/* NAND interface */
GPMI_D0 | VE_3_3V | PULLUP(1),
GPMI_D1 | VE_3_3V | PULLUP(1),
GPMI_D2 | VE_3_3V | PULLUP(1),
GPMI_D3 | VE_3_3V | PULLUP(1),
GPMI_D4 | VE_3_3V | PULLUP(1),
GPMI_D5 | VE_3_3V | PULLUP(1),
GPMI_D6 | VE_3_3V | PULLUP(1),
GPMI_D7 | VE_3_3V | PULLUP(1),
GPMI_READY0 | VE_3_3V | PULLUP(0), /* external PU */
GPMI_CE0N | VE_3_3V | PULLUP(1),
GPMI_RDN | VE_3_3V | PULLUP(1),
GPMI_WRN | VE_3_3V | BITKEEPER(1),
GPMI_ALE | VE_3_3V | PULLUP(1),
GPMI_CLE | VE_3_3V | PULLUP(1),
GPMI_RESETN | VE_3_3V | PULLUP(0), /* external PU */
/* Network interface */
/*
* Note: To setup the external phy in a manner the baseboard
* supports, its configuration is divided into a small part here in
* the CPU card setup and the remaining configuration in the baseboard
* file.
* Here: Switch on the power supply to the external phy, but keep its
* reset line low.
*/
#include <asm/armlinux.h>
#include <asm/mmu.h>
#include <generated/mach-types.h>
#define MX28EVK_FEC_PHY_RESET_GPIO 141
/* setup the CPU card internal signals */
static const uint32_t mx28evk_pads[] = {
/* duart */
PWM0_DUART_RX | VE_3_3V,
PWM1_DUART_TX | VE_3_3V,
/* fec0 */
ENET_CLK | VE_3_3V | BITKEEPER(0),
ENET0_MDC | VE_3_3V | PULLUP(1),
ENET0_MDIO | VE_3_3V | PULLUP(1),
ENET0_TXD0 | VE_3_3V | PULLUP(1),
ENET0_TXD1 | VE_3_3V | PULLUP(1),
ENET0_TX_EN | VE_3_3V | PULLUP(1),
ENET0_TX_CLK | VE_3_3V | BITKEEPER(0),
ENET0_RXD0 | VE_3_3V | PULLUP(1),
ENET0_RXD1 | VE_3_3V | PULLUP(1),
ENET0_RX_EN | VE_3_3V | PULLUP(1),
/* send a "good morning" to the ext. phy 0 = reset */
ENET0_RX_CLK_GPIO | VE_3_3V | PULLUP(0) | GPIO_OUT | GPIO_VALUE(0),
/* phy power control 1 = on */
SSP1_D3_GPIO | VE_3_3V | PULLUP(0) | GPIO_OUT | GPIO_VALUE(0),
/* mmc0 */
/* duart */
FUNC(2) | PORTF(3, 2) | VE_3_3V,
FUNC(2) | PORTF(3, 3) | VE_3_3V,
/* mmc0 */
SSP0_D0 | VE_3_3V | PULLUP(1),
SSP0_D1 | VE_3_3V | PULLUP(1),
SSP0_D2 | VE_3_3V | PULLUP(1),
SSP0_D3 | VE_3_3V | PULLUP(1),
SSP0_D4 | VE_3_3V | PULLUP(1),
SSP0_D5 | VE_3_3V | PULLUP(1),
SSP0_D6 | VE_3_3V | PULLUP(1),
SSP0_D7 | VE_3_3V | PULLUP(1),
SSP0_CMD | VE_3_3V | PULLUP(1),
SSP0_CD | VE_3_3V | PULLUP(1),
SSP0_SCK | VE_3_3V | BITKEEPER(0),
/* MCI slot power control 1 = off */
PWM3_GPIO | VE_3_3V | GPIO_OUT | GPIO_VALUE(0),
};
static struct mxs_mci_platform_data mci_pdata = {
.caps = MMC_MODE_8BIT,
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34, /* fixed to 3.3 V */
.f_min = 400 * 1000,
.f_max = 25000000,
};
static int cfa10036_mem_init(void)
{
arm_add_mem_device("ram0", IMX_MEMORY_BASE, 128 * 1024 * 1024);
* Part II of phy's initialization
* Setup phy's mode to '111'
*/
/*
* force the mod pins to a specific level
* '111' means: "All capable. Auto-negotiation enabled".
* For other values refer LAN8710's datasheet,
* chapter "Mode Bus - MODE[2:0]"
*/
ENET0_RXD0_GPIO | VE_3_3V | GPIO_OUT | GPIO_VALUE(1), /* MOD0 */
ENET0_RXD1_GPIO | VE_3_3V | GPIO_OUT | GPIO_VALUE(1), /* MOD1 */
ENET0_RX_EN_GPIO | VE_3_3V | GPIO_OUT | GPIO_VALUE(1), /* MOD2 */
/* release the reset ('mod' pins get latched) */
ENET0_RX_CLK_GPIO | VE_3_3V | BITKEEPER(0) | GPIO_OUT | GPIO_VALUE(1),
/* right now the 'mod' pins are in their native mode */
ENET0_RXD0 | VE_3_3V | PULLUP(0),
ENET0_RXD1 | VE_3_3V | PULLUP(0),
ENET0_RX_EN | VE_3_3V | PULLUP(0),
/* Debug UART, available at card connector UART1 */
AUART0_CTS_DUART_RX | VE_3_3V | STRENGTH(S8MA),
AUART0_RTS_DUART_TX | VE_3_3V | STRENGTH(S8MA),
AUART0_RX_DUART_CTS | VE_3_3V | STRENGTH(S8MA),
AUART0_TX_DUART_RTS | VE_3_3V | STRENGTH(S8MA),
/* Application UART, available at connector UART2 */
AUART1_RX | VE_3_3V | BITKEEPER(0),
AUART1_TX | VE_3_3V | BITKEEPER(0),
AUART1_CTS | VE_3_3V | PULLUP(1),
