void tmr_test(void)
{
// Create a timer object
tmr_t tmr;
// Initialise PIO
BIT_SET_HI(PORT_LED_O, BIT_LED_O);
BIT_SET_HI(DDR_LED_O, BIT_LED_O);
// Initialise module
pit_init();
// Enable global interrupts
sei();
// Start timer with a 1s timeout
tmr_start(&tmr, TMR_MS_TO_TICKS(1000));
for(;;)
{
// Wait until timer has expired
while(!tmr_has_expired(&tmr))
{
;
}
// Restart timer
tmr_restart(&tmr);
// Toggle LED
LED_TOGGLE();
}
}
void hdlc_test(void)
{
u8_t data;
// Enable RS-485 PIO for loopback operation
BIT_SET_HI(PORT_RS485_TX_EN_O, BIT_RS485_TX_EN_O);
BIT_SET_HI(DDR_RS485_TX_EN_O, BIT_RS485_TX_EN_O);
BIT_SET_LO(PORT_RS485_RX_EN_O, BIT_RS485_RX_EN_O);
BIT_SET_HI(DDR_RS485_RX_EN_O, BIT_RS485_RX_EN_O);
// Initialise modules
uart0_init();
uart1_init();
printf_init();
hdlc_init(&hdlc_on_rx_frame);
// Enable global interrupts
sei();
// Send an HDLC packet
data = 0x55;
hdlc_tx_frame(&data,1);
// Process received data
for(;;)
{
if(uart1_get_rx_byte(&data))
{
PRINTF("%02X ", data);
// Feed received data to HDLC layer
hdlc_on_rx_byte(data);
}
}
}
void tmr0_init(void)
{
// Select asynchronous timer 0 operation to use external 32.768 kHz crystal
BIT_SET_HI(ASSR,AS0);
// Reset time
TCNT0 = 0;
// Calculate and set period
OCR0 = (uint16)DIV(((F_RTC/8)*TMR0_PERIOD_MS),1000) - 1;
/* Start timer 0 with clock prescaler CLK/8 and CTC Mode ("Clear Timer on Compare")*/
/* Resolution is 244.14 us */
/* Maximum period is 62.5 ms */
TCCR0 = TMR0_TCCR0_VALUE;
// Wait for "update busy" flags to clear
while(ASSR&((1<<TCN0UB)|(1<<OCR0UB)|(1<<TCR0UB)))
{
;
}
// Enable interrupt on compare match
BIT_SET_HI(TIMSK,OCIE0);
}
int main(void)
{
// Initialise IO pins
PORTB = (1<<BIT_SPI_SS_O)|(1<<BIT_FLASH_CS_O)|(1<<BIT_SW_IP)
|(0<<BIT_LED_O)|(1<<BIT_BUZZER_O);
DDRB = (1<<BIT_SPI_SS_O)|(1<<BIT_FLASH_CS_O)|(0<<BIT_SW_IP)
|(1<<BIT_LED_O)|(1<<BIT_BUZZER_O);
PORTD = (0<<BIT_RS485_TX_EN_O)|(1<<BIT_RS485_RX_EN_O)
|(0<<BIT_RTS_I)|(0<<BIT_CTS_O);
DDRD = (1<<BIT_RS485_TX_EN_O)|(1<<BIT_RS485_RX_EN_O)
|(0<<BIT_RTS_I)|(1<<BIT_CTS_O);
// Initialise modules
tmr0_init();
// Enable external interrupt 0 on falling edge
EICRA = (0<<ISC31)|(0<<ISC30)|(0<<ISC21)|(0<<ISC20)
|(0<<ISC11)|(0<<ISC10)|(1<<ISC01)|(0<<ISC00);
EIMSK = (0<<INT7)|(0<<INT6)|(0<<INT5)|(0<<INT4)
|(0<<INT3)|(0<<INT2)|(0<<INT1)|(1<<INT0);
// Select sleep mode
set_sleep_mode(SLEEP_MODE_PWR_SAVE);
// Disable On Chip Debug System, otherwise main clock source stays enabled
// See p.48 of ATmega128 datasheet
BIT_SET_HI(MCUCSR,JTD);
// This bit must be set twice within four cycles to change its value.
// See p.258 of ATmega128 datasheet
BIT_SET_HI(MCUCSR,JTD);
// Disable Analog Comparator to reduce power consumption
BIT_SET_HI(ACSR,ACD);
// Enable interrupts
sei();
// Loop indefinitely
for(;;)
{
// Wait at least one TOSC1 cycle for interrupt logic to reset,
// otherwise the device will fail to wake up when sleep mode is entered
TMR0_vWaitOneTOSC1();
// Go into sleep mode until an event wakes up the CPU
sleep_mode();
// See if switch is pressed
if(SW_IS_PRESSED())
{
LED_ON();
}
else
{
LED_OFF();
}
}
}
u8_t uart1_tx_data(const u8_t* data, u8_t bytes_to_send)
{
u8_t bytes_buffered = 0;
u8_t index;
while(bytes_to_send)
{
// Calculate next pointer position
index = uart1_tx_in;
UART1_NEXT_INDEX(index, UART1_TX_BUFFER_SIZE);
// Make sure there is space available in buffer
if(index == uart1_tx_out)
{
break;
}
// Insert data into buffer
uart1_tx_buffer[uart1_tx_in] = *data++;
// Advance pointer
uart1_tx_in = index;
// Next byte
bytes_buffered++;
bytes_to_send--;
}
// Make sure transmit process is started by enabling interrupt
BIT_SET_HI(UCSR1B, UDRIE);
return bytes_buffered;
}
void tmr_poll_start(u16_t start_val)
{
TCNT1 = start_val;
// Clear timer overflow flag
BIT_SET_HI(TIFR, TOV1);
}
void at45db041b_test(void)
{
u8_t status;
u16_t counter;
// Initialise PIO
BIT_SET_HI(PORT_SFLASH_CS_O, BIT_SFLASH_CS_O);
BIT_SET_HI(DDR_SFLASH_CS_O, BIT_SFLASH_CS_O);
// Initialise modules
spi_init();
uart0_init();
printf_init();
at45db041b_init();
// Enable global interrupts
sei();
// See if Serial FLASH is present
status = at45db041b_get_status();
if((status & AT45DB041B_DENSITY_MASK) != AT45DB041B_DENSITY)
{
PRINTF("Error! AT45DB041B not present. Status = 0x%02X\n", status);
return;
}
// Write a page of Serial FLASH
for(counter = 0; counter<AT45DB041B_PAGE_SIZE; counter++)
{
page[counter] = (u8_t)(counter&0xff);
}
at45db041b_write_page(AT45DB041B_PAGES-1, page);
// Read a page of Serial FLASH
at45db041b_read_page(AT45DB041B_PAGES-1, page);
// Report content of page
for(counter = 0; counter<AT45DB041B_PAGE_SIZE; counter++)
{
PRINTF("%02X ", page[counter]);
if((counter&0x0F) == 0x0F)
{
PRINTF("\n");
}
}
}
void tmr_poll_wait(u16_t start_val)
{
TCNT1 = start_val;
// Clear timer overflow flag
BIT_SET_HI(TIFR, TOV1);
// Wait until timer overflows
LOOP_UNTIL_BIT_IS_HI(TIFR, TOV1);
}
/* _____GLOBAL FUNCTIONS_____________________________________________________ */
void spi_init(void)
{
// Enable SPI pins
BIT_SET_HI(PORT_SPI, BIT_SPI_SS);
BIT_SET_LO(DDR_SPI, BIT_SPI_SS);
BIT_SET_HI(PORT_SPI, BIT_SPI_SCK);
BIT_SET_HI(DDR_SPI, BIT_SPI_SCK);
BIT_SET_HI(PORT_SPI, BIT_SPI_MOSI);
BIT_SET_HI(DDR_SPI, BIT_SPI_MOSI);
BIT_SET_LO(PORT_SPI, BIT_SPI_MISO);
BIT_SET_LO(DDR_SPI, BIT_SPI_MISO);
// Configure and enable SPI peripheral
SPCR = (0<<SPIE)|(1<<SPE)|(0<<DORD)|(1<<MSTR)
|(0<<CPOL)|(0<<CPHA)|(0<<SPR1)|(0<<SPR0);
SPSR = (0<<SPI2X);
}
u08 CHandler::test() {
u08 cca, cca_cnt, mode;
cca = 0;
cca_cnt = 0;
BIT_SET_LO(PORTD, 5);
_delay_us(10);
BIT_SET_HI(PORTD, 5);
mode = cc1101->readReg(CC1101_MARCSTATE, CC1101_STATUS_REGISTER) & 0x1F;
if (mode == MARC_STATE_TXFIFO_UV) {
cc1101->cmdStrobe(CC1101_SFTX);
}
if (mode == MARC_STATE_RXFIFO_OV) {
cc1101->cmdStrobe(CC1101_SFRX);
}
// ================= wait for IDLE MODE ==================
if ((mode == MARC_STATE_IDLE || mode == MARC_STATE_RX)) {
cca_cnt = 0;
// ================= SET RX MODE==========================
cc1101->cmdStrobe(CC1101_SRX);
// =================== wait 800us for RX MODE ============
do {
mode = cc1101->readReg(CC1101_MARCSTATE, CC1101_STATUS_REGISTER) & 0x1F;
cca_cnt++;
_delay_us(10); // IDLE TO RX takes 800us page 54 in datasheet
} while ((mode != MARC_STATE_RX) && (cca_cnt < 200));
if (cca_cnt >= 200) {
cc1101->cmdStrobe(CC1101_SIDLE); // FORCE IDLE MODE
return false;
}
//================= Send Packet to FIFO ==================
cc1101->writeReg(CC1101_TXFIFO, sizeof(TAG::sRfTag));
cc1101->writeBurstReg(CC1101_TXFIFO, (u08*) &tag, sizeof(TAG::sRfTag));
mode = cc1101->readReg(CC1101_MARCSTATE, CC1101_STATUS_REGISTER) & 0x1F;
cc1101->rssiValidWait();
cc1101->cmdStrobe(CC1101_STX);
while (BIT_IS_HI(READ_GD0,PIN_GD0))
;
// ================= Wait 725 us for IDLE MODE ===========
cca_cnt = 0;
do {
mode = cc1101->readReg(CC1101_MARCSTATE, CC1101_STATUS_REGISTER) & 0x1F;
_delay_us(10); // TX to IDle with calibration - 725 us
} while ((mode != MARC_STATE_IDLE));
return true;
}
return false;
}
bool_t uart1_tx_byte(u8_t data)
{
u8_t index = uart1_tx_in;
// Calculate next pointer position
UART1_NEXT_INDEX(index, UART1_TX_BUFFER_SIZE);
// Make sure there is space available in buffer
if(index == uart1_tx_out)
{
return FALSE;
}
// Insert data into buffer
uart1_tx_buffer[uart1_tx_in] = data;
// Advance pointer
uart1_tx_in = index;
// Make sure transmit process is started by enabling interrupt
BIT_SET_HI(UCSR1B, UDRIE);
return TRUE;
}
void spi_init2(u32_t bit_rate, u8_t spi_mode, bool_t data_order_lsb)
{
u8_t spcr;
u32_t actual_bit_rate;
u8_t divisor;
// Default values for SPCR
spcr = (0<<SPIE)|(1<<SPE)|(0<<DORD)|(1<<MSTR)
|(0<<CPOL)|(0<<CPHA)|(0<<SPR1)|(0<<SPR0);
// Set data order
if(data_order_lsb == TRUE)
{
BIT_SET_HI(spcr, DORD);
}
// Set SPI Mode (0,1,2 or 3)
spcr |= (spi_mode&3) << CPHA;
// Select clock divisor that generates a bit rate closest to the desired bit rate (equal or less)
actual_bit_rate = F_CPU;
divisor = 1;
do
{
actual_bit_rate >>= 1;
divisor <<= 1;
// Stop if divisor reaches maximum
if(divisor == 128)
{
break;
}
}
while (actual_bit_rate > bit_rate);
switch(divisor)
{
case 2 : spcr |= (0<<SPR1)|(0<<SPR0);
BIT_SET_HI(SPSR, SPI2X);
break;
case 4 : spcr |= (0<<SPR1)|(0<<SPR0);
BIT_SET_LO(SPSR, SPI2X);
break;
case 8 : spcr |= (0<<SPR1)|(1<<SPR0);
BIT_SET_HI(SPSR, SPI2X);
break;
case 16 : spcr |= (0<<SPR1)|(1<<SPR0);
BIT_SET_LO(SPSR, SPI2X);
break;
case 32 : spcr |= (1<<SPR1)|(0<<SPR0);
BIT_SET_HI(SPSR, SPI2X);
break;
case 64 : spcr |= (1<<SPR1)|(0<<SPR0);
BIT_SET_LO(SPSR, SPI2X);
break;
case 128 : spcr |= (1<<SPR1)|(1<<SPR0);
BIT_SET_LO(SPSR, SPI2X);
break;
default:
break;
}
SPCR = spcr;
}
