/******************************************************************************
* Function: void UsbToPHDComCB(UINT8 USB_Event, void * val)
*
* PreCondition: None
*
* Input: None
*
* Output: None
*
* Side Effects: None
*
* Overview: This routine is called from the transport layer informing about
* its events
*
* Note:
*
*****************************************************************************/
void UsbToPHDComCB(UINT8 USB_Event, void * val)
{
UINT16 *size;
APDU *ptr;
UINT16 length, choice;//, count;
#if defined(__18CXX)
UINT16 *PTR;
#elif defined(__C30__) || defined __XC16__
//UINT16 *PTR;
#elif defined(__PIC32MX__)
UINT32 *PTR;
#endif
switch(USB_Event)
{
case USB_APP_SEND_COMPLETE:
if(PhdComState == PHD_COM_STATE_ASSOC_CFG_SENDING_CONFIG)
{
PhdComState = PHD_COM_STATE_ASSOC_CFG_WAITING_APPROVAL;
PhdConfigurationTimeoutStatus = TIMEOUT_ENABLED;
PhdConfigurationTimeout = CONFIGURATION_TIMEOUT;
}
break;
case USB_APP_DATA_RECEIVED:
USBDevicePHDCReceiveData(PHDC_BULK_OUT_QOS,pPhdAppBuffer,0); //get ready to receive
PHDAppDataRxHandler(pPhdAppBuffer);
break;
case USB_APP_GET_TRANSFER_SIZE:
size=(UINT16*)val;
ptr = (APDU*)pPhdAppBuffer;
length = BYTE_SWAP16(ptr->length);
choice = BYTE_SWAP16(ptr->choice);
*size = length + 4;
//PhdAppBufferOffset = 0;
break;
default:
break;
}//End of switch(USB_Event)
}
void HSCSI_ISR_Mailbox(PHSCSI_INSTANCE_DATA Id)
{
HSCSI_EVENT_CONTEXT *p_context;
STATUS status;
HSCSI_TRACE_ENTRY(HSCSI_ISR_Mailbox);
// Save the contents of outgoing mailbox register 0.
Id->HSCSI_mailbox_message.mailbox[0] = Read_ISP1040(Id, HSCSI_MAILBOX_0);
// Check for an asynchronous event.
switch(Id->HSCSI_mailbox_message.mailbox[0])
{
case 0x8001:
// Asynchronous event Reset detected
HSCSI_Handle_Async_Event(Id, HSCSI_ACTION_HANDLE_OTHER_AE,
Id->HSCSI_mailbox_message.mailbox[0]);
HSCSI_Log_Error(HSCSI_ERROR_TYPE_WARNING,
"HSCSI_ISR_Mailbox",
"Asynchronous event Reset detected",
0,
Id->HSCSI_mailbox_message.mailbox[0]);
goto Clear_Semaphore_Lock;
case 0x8002:
// Asynchronous event System Error detected
// usually get this error when an address error occurs,
// not a physical address, not mapped memory
// Save the contents of the outgoing mailbox registers for Debug
Id->HSCSI_mailbox_message.mailbox[1] = Read_ISP1040(Id, HSCSI_MAILBOX_1);
Id->HSCSI_mailbox_message.mailbox[2] = Read_ISP1040(Id, HSCSI_MAILBOX_2);
Id->HSCSI_mailbox_message.mailbox[3] = Read_ISP1040(Id, HSCSI_MAILBOX_3);
Id->HSCSI_mailbox_message.mailbox[4] = Read_ISP1040(Id, HSCSI_MAILBOX_4);
Id->HSCSI_mailbox_message.mailbox[5] = Read_ISP1040(Id, HSCSI_MAILBOX_5);
Id->HSCSI_mailbox_message.mailbox[6] = Read_ISP1040(Id, HSCSI_MAILBOX_6);
Id->HSCSI_mailbox_message.mailbox[7] = Read_ISP1040(Id, HSCSI_MAILBOX_7);
HSCSI_Log_Error(HSCSI_ERROR_TYPE_FATAL,
"HSCSI_ISR_Mailbox",
"Asynchronous event System Error detected",
0,
Id->HSCSI_mailbox_message.mailbox[0]);
goto Clear_Semaphore_Lock;
case 0x8003:
// Asynchronous event Request Transfer error
// HSCSI_Handle_Async_Event(Id, HSCSI_ACTION_HANDLE_OTHER_AE,
// Id->HSCSI_mailbox_message.mailbox[0]);
HSCSI_Log_Error(HSCSI_ERROR_TYPE_FATAL,
"HSCSI_ISR_Mailbox",
"Asynchronous event Request Transfer error detected",
0,
Id->HSCSI_mailbox_message.mailbox[0]);
goto Clear_Semaphore_Lock;
case 0x8004:
// Asynchronous event Response Transfer error
// HSCSI_Handle_Async_Event(Id, HSCSI_ACTION_HANDLE_OTHER_AE,
// Id->HSCSI_mailbox_message.mailbox[0]);
HSCSI_Log_Error(HSCSI_ERROR_TYPE_FATAL,
"HSCSI_ISR_Mailbox",
"Asynchronous event Response Transfer error detected",
0,
Id->HSCSI_mailbox_message.mailbox[0]);
goto Clear_Semaphore_Lock;
case 0x8005:
// Asynchronous event Request queue wakeup
// Not currently using this feature
HSCSI_Log_Error(HSCSI_ERROR_TYPE_FATAL,
"HSCSI_ISR_Mailbox",
"Asynchronous event Request queue wakeup detected",
0,
Id->HSCSI_mailbox_message.mailbox[0]);
goto Clear_Semaphore_Lock;
case 0x8006:
// Execution timeout reset
HSCSI_Handle_Async_Event(Id, HSCSI_ACTION_HANDLE_OTHER_AE,
Id->HSCSI_mailbox_message.mailbox[0]);
HSCSI_Log_Error(HSCSI_ERROR_TYPE_WARNING, "HSCSI_ISR_Mailbox",
"Execution Timeout Reset detected", 0,
Id->HSCSI_mailbox_message.mailbox[0]);
goto Clear_Semaphore_Lock;
case 0x8020:
// Asynchronous event SCSI command Complete (fast posting)
// Send a message to the task that is waiting
case 0x8021:
// Asynchronous event CTIO Complete. (fast posting)
// Send a message to the task that is waiting
#if defined(HSCSI_DEBUG)
// save these values for DEBUG later
Id->HSCSI_mailbox_message.mailbox[1] = Read_ISP1040(Id, HSCSI_MAILBOX_1);
Id->HSCSI_mailbox_message.mailbox[2] = Read_ISP1040(Id, HSCSI_MAILBOX_2);
#endif
// Get pointer to context for waiting task.
#if 0 // NOTE: This code worked prior to the V3 IDE...
p_context = (HSCSI_EVENT_CONTEXT*)(UNSIGNED)
(BYTE_SWAP16(Read_ISP1040(Id, HSCSI_MAILBOX_2)) |
BYTE_SWAP16(Read_ISP1040(Id, HSCSI_MAILBOX_1)) << 16);
#else
p_context = (HSCSI_EVENT_CONTEXT*)(UNSIGNED)
(*(U16 *)((UNSIGNED)Id->Regs + HSCSI_MAILBOX_2) |
*(U16 *)((UNSIGNED)Id->Regs + HSCSI_MAILBOX_1) << 16);
#endif
HSCSI_PRINT_HEX(TRACE_L8, "\n\rFast Post context = ", (U32)p_context);
// Clear the semaphore lock.
// This lets the RISC know that the outgoing mailbox registers
// are now available.
Write_ISP1040(Id, HSCSI_SEMAPHORE, 0);
// The command completed successfully, so set the status
// in the status IOCB.
// if (Id->HSCSI_mailbox_message.mailbox[0] == 0x8021)
// ((PIOCB_CTIO_TYPE_2) &p_context->status_iocb)->status =
// STATUS_COMPLETE;
// else
// {
p_context->status_iocb.SCSI_status = SCSI_STATUS_GOOD;
p_context->status_iocb.state_flags =
BYTE_SWAP16(IOCB_STATE_FLAGS_XFER_COMPLETE);
// }
HSCSI_ASSERT(Id == p_context->Id, "HSCSI_ISR_Mailbox Fast Post");
// Send a message to HSCSI_Event_Task.
// The action field of the context will tell HSCSI_Event_Task
// what to do next.
status = NU_Send_To_Queue(&Id->HSCSI_event_queue,
&p_context, // message is pointer to context
1, // size is one UNSIGNED
NU_NO_SUSPEND);
if (status != NU_SUCCESS)
HSCSI_Log_Error(HSCSI_ERROR_TYPE_FATAL,
"HSCSI_ISR_Mailbox",
"NU_Send_To_Queue failed",
status,
(UNSIGNED)Id);
return;
default:
// It's not an asynchronous event
break;
} // switch
// Continue if it's not an asynchronous event
// Assume that a task is waiting for a mailbox command to complete.
// Save the contents of the outgoing mailbox registers.
Id->HSCSI_mailbox_message.mailbox[1] = Read_ISP1040(Id, HSCSI_MAILBOX_1);
Id->HSCSI_mailbox_message.mailbox[2] = Read_ISP1040(Id, HSCSI_MAILBOX_2);
Id->HSCSI_mailbox_message.mailbox[3] = Read_ISP1040(Id, HSCSI_MAILBOX_3);
// Clear the semaphore lock.
// This lets the RISC know that the outgoing mailbox registers
// are now available.
Write_ISP1040(Id, HSCSI_SEMAPHORE, 0);
HSCSI_PRINT_STRING(TRACE_L8, "\n\rMB Command Complete");
// Send contents of mailboxes to waiting task.
status = NU_Send_To_Queue(&Id->HSCSI_mailbox_queue,
&Id->HSCSI_mailbox_message,
sizeof(HSCSI_MAILBOX_MESSAGE) / sizeof(UNSIGNED), // size is an entire MB struct
NU_NO_SUSPEND);
if (status != NU_SUCCESS)
{
HSCSI_Log_Error(HSCSI_ERROR_TYPE_FATAL,
"HSCSI_ISR_Mailbox",
"NU_Send_To_Queue failed",
status,
(UNSIGNED)Id);
return;
}
return;
Clear_Semaphore_Lock:
// Clear the semaphore lock.
// This lets the RISC know that the outgoing mailbox registers
// are now available.
Write_ISP1040(Id, HSCSI_SEMAPHORE, 0);
} // HSCSI_ISR_Mailbox
void task_0(void) {
unsigned key = 0;
unsigned i,s;
U16 j; // Module Select Bits
unsigned cMsDelay=1;
unsigned idx;
TRACE_ENTRY(task_0);
// start on a fresh line
printf("\n\r");
DrawScreen();
/* Task0 forever loop */
while(1) {
//cMsDelay=1;
switch (key = getch()) {
// The first set of commands are general purpose commands
// for all projects
case 'X': /* X - cause address exception and return to boot code */
printf("Exit with exception\r\n\r\n");
unsigned long *d = ( unsigned long * ) 0x1;
*d = 0xFFFF0000;
break;
case ' ': /* SPACEBAR - redraw the screen */
DrawScreen();
break;
case 0x08: /* BACKSPACE */
case 0x09: /* TAB */
case 0x1B: /* ESC */
printf(" \n\r");
//printf(" /008");
break;
case 0x0D: /* ENTER */
case 0x0A: /* or the real ENTER */
printf("\n\r");
break;
#if defined(HSCSI_DEBUG) && defined(_DEBUG)
case '0':
case '1':
case '2':
case '3':
case '4':
case '5':
case '6':
case '7':
case '8':
case '9':
// Set the Global TraceLevel index to the number specified
idx = key - 0x30;
debug_set:
printf("\n\rTraceLevel[%d] = %d",
index[idx], TraceLevel[index[idx]]);
break;
case '!':
idx = 10;
goto debug_set;
case '@':
idx = 11;
goto debug_set;
case '#':
idx = 12;
goto debug_set;
case '+':
// Increment the Global TraceLevel
TraceLevel[index[idx]]++;
printf("\n\rTraceLevel[%d] = %d",
index[idx], TraceLevel[index[idx]]);
break;
case '-':
// Increment the Global TraceLevel
TraceLevel[index[idx]]--;
printf("\n\rTraceLevel[%d] = %d",
index[idx], TraceLevel[index[idx]]);
break;
case 'a':
// Set the Global TraceLevel for all 15 to max
for (idx = 0; idx < 15; idx++)
{
TraceLevel[index[idx]] = TRACE_ALL_LVL;
printf("\n\rTraceLevel[%d] = %d",
index[idx], TraceLevel[index[idx]]);
}
break;
case 'm':
// Set the Global TraceLevel for all 15 to min
for (idx = 0; idx < 15; idx++)
{
TraceLevel[index[idx]] = TRACE_L2;
printf("\n\rTraceLevel[%d] = %d",
index[idx], TraceLevel[index[idx]]);
}
break;
#endif
// Oos specific command extensions
case 'i':
TRACE_STRING(TRACE_L2, "\n\rOs:Initialize called\n\r");
Os::Initialize();
break;
case 'n':
printf_at(7,0,"Interrupt counters\r\n");
for (i=Interrupt::tyFirst; i < Interrupt::tyLast; i++) {
printf("%04x", (int)Interrupt::aN[i]);
printf(" ");
}
break;
case 'b':
printf_at(7,0,"Base registers\r\n");
Print_Dump((unsigned long*)GT_CPU_CONFIG_REG, 64);
break;
case 'd':
printf_at(7,0,"I2O registers\r\n");
Print_Dump((unsigned long*)(GT_I2O_BASE), 32);
break;
case 'D':
printf_at(7,0,"DMA registers\r\n");
Print_Dump((unsigned long*)(GT_DMA_CH0_COUNT_REG), 32);
break;
case 'p':
printf_at(7,0,"PCI registers\r\n");
Print_Dump((unsigned long*)(GT_PCI_COMMAND_REG), 64);
break;
case 'u':
printf_at(7,0,"PCI internal registers\r\n");
for (i=0x80000000; i < 0x80000120; i+= 4) {
if (i % 0x10 == 0) {
printf("\n\r");
printf("%04x", i & 0xFF);
}
printf(" ");
*(unsigned long*)(GT_PCI_CONFIG_ADDR_REG) = BYTE_SWAP32(i);
printf("%08x", BYTE_SWAP32(*(unsigned long*)(GT_PCI_CONFIG_DATA_REG)));
}
break;
case 'U':
printf_at(7,0,"ISP1040/PCI internal registers\r\n");
for (i=0x80004000; i < 0x80004100; i+= 4) { // slot 6 = 80003000
if (i % 0x10 == 0) {
printf("\n\r");
printf("%04x", i & 0xFF);
}
printf(" ");
*(unsigned long*)(GT_PCI_CONFIG_ADDR_REG) = BYTE_SWAP32(i);
// printf("%08x", BYTE_SWAP32(*(unsigned long*)(GT_PCI_CONFIG_DATA_REG)));
printf("%04x%04x", (*(unsigned long*)(GT_PCI_CONFIG_DATA_REG)&0xffff),
(*(unsigned long*)(GT_PCI_CONFIG_DATA_REG)>>16));
}
break;
// FCP specific command extensions
case 't':
extern void S_Test_Unit_Ready(U32 drive_no);
S_Test_Unit_Ready(0);
break;
case 'y':
// spare
break;
#if !defined(NIC_TEST_BUILD)
case 'h':
void S_Read_Test(U32 drive_no);
S_Read_Test(0); // drive 0
break;
case 'j':
void S_Sts_Read_Test(U32 drive_no);
S_Sts_Read_Test(TestVdn); // Virtual Device
break;
case 's':
{
// defined in the DriveMonitor
extern void S_Scan_For_Drives(Message *pMsg);
S_Scan_For_Drives(NULL);
s=1; // keep track of start/stop
}
break;
case 'S':
s=s^0x0001;
extern void S_Stop_Drive(U32 drive_no, unsigned s);
S_Stop_Drive(0,s);
break;
#endif
case 'r':
printf_at(7,0,"ISP 1 PCI registers\r\n");
for (i=0x80004800; i < 0x80004840; i+= 4) {
if (i % 0x10 == 0) {
printf("\n\r");
printf("%04x", i & 0xFF);
}
printf(" ");
*(unsigned long*)(GT_PCI_CONFIG_ADDR_REG) = BYTE_SWAP32(i);
printf("%08x", *(unsigned long*)(GT_PCI_CONFIG_DATA_REG));
}
break;
case 'R':
printf_at(7,0,"ISP 2 PCI registers\r\n");
for (i=0x80003000; i < 0x80003040; i+= 4) {
if (i % 0x10 == 0) {
printf("\n\r");
printf("%04x", i & 0xFF);
}
printf(" ");
*(unsigned long*)(GT_PCI_CONFIG_ADDR_REG) = BYTE_SWAP32(i);
printf("%08x", *(unsigned long*)(GT_PCI_CONFIG_DATA_REG));
}
break;
case 'z':
printf_at(7,0,"ISP 1 registers\r\n");
for (i=0; i < 0x100; i+= 2) {
if (i % 0x10 == 0) {
printf("\n\r");
printf("%04x", i & 0xFF);
}
printf(" ");
printf("%04x",
BYTE_SWAP16(*((U16*)((UNSIGNED)(ISP_memory_base_address | 0xA0000000) + i))));
}
break;
case 'Z':
printf_at(7,0,"ISP 2 registers\r\n");
for (i=0; i < 0x100; i+= 2) {
if (i % 0x10 == 0) {
printf("\n\r");
printf("%04x", i & 0xFF);
}
printf(" ");
printf("%04x",
BYTE_SWAP16(*((U16*)((UNSIGNED)(ISP_memory_base_address2 | 0xA0000000) + i))));
}
break;
case 'H':
printf_at(7,0,"ISP 3 registers\r\n");
for (i=0;i<0x100;i+=2) {
if (i%0x10==0) {
printf("\n\r");
printf("%04x",i&0xff);
}
printf(" ");
printf("%04x",BYTE_SWAP16(*((U16*)((UNSIGNED)(ISP_memory_base_address3 | 0xa0000000)+i))));
}
break;
case 'f':
U16 *ispcs = (U16 *)((ISP_memory_base_address3 | K1BASE)+HSCSI_CONFIG_1);
U16 *isphccr = (U16 *)((ISP_memory_base_address3 | K1BASE)+HSCSI_HCCR);
// Clear RISC interrupt (FCP_Mailbox_Wait_Ready_Intr) if needed
*isphccr=BYTE_SWAP16((UNSIGNED)HCCRPAUSERISC); // Pause RISC
printf_at(7,0,"HSCSI PBIU/RISC registers\r\n");
j = BYTE_SWAP16(*ispcs)&0x00f7;
*ispcs=BYTE_SWAP16(j); // Set ISP Control/Status register
for (i=0x00; i<0x100; i+=2) {
if (!(i % 0x10)) {
printf("\n\r");
printf("%04x",i&0xff);
}
printf(" ");
printf("%04x", BYTE_SWAP16(*((U16*)((UNSIGNED)(ISP_memory_base_address3 | K1BASE)+i))));
}
printf("\r\n");
*isphccr=BYTE_SWAP16((UNSIGNED)HCCRRLSRISC); // Unpause RISC
break;
case 'F':
U16 *ispcs2=(U16*)((ISP_memory_base_address3 | K1BASE)+HSCSI_CONFIG_1);
U16 *isphccr2=(U16*)((ISP_memory_base_address3|K1BASE)+HSCSI_HCCR);
U16 *sxp=(U16*)((ISP_memory_base_address3|K1BASE)+0xa4);
*isphccr2=BYTE_SWAP16((UNSIGNED)HCCRPAUSERISC); // Pause RISC
printf_at(7,0,"HSCSI PBIU/SXP registers\r\n");
j = BYTE_SWAP16(*ispcs2)|0x0008; // SXP select
*ispcs2=BYTE_SWAP16(j); // ISP Config 1 register
// *sxp = BYTE_SWAP16(0x0c00); // SXP override
for (i=0x00;i<0x100; i+=2) {
if (!(i % 0x10)) {
printf("\n\r");
printf("%04x",i&0xff);
}
printf(" ");
printf("%04x",BYTE_SWAP16(*((U16*)((UNSIGNED)(ISP_memory_base_address3 | K1BASE)+i))));
}
printf("\r\n");
j = j&0x00f7; // SXP select bit off
*ispcs2=BYTE_SWAP16(j);
*isphccr2=BYTE_SWAP16((UNSIGNED)HCCRRLSRISC); // Unpause RISC
break;
case 'x':
// x - cause address exception
// and return to boot code
unsigned long *g = ( unsigned long * ) 0x1;
*g = 0xFFFF0000;
break;
case 'q':
// scan all PCI slots for devices
// print only the devices found
printf("PCI Devices:\n\r");
for (i = 0; i < 31; i++) {
U32 reg;
reg = GetPciReg(0, i, 0, 0);
if (reg == 0xffffffff)
continue;
printf("S:%02d = %08x\n\r", i, reg);
}
break;
default:
printf("%c", key);
break;
} /* switch (key = Get_Char()) */
NU_Sleep(cMsDelay);
cMsDelay=5;
} /* while(1) */
}
