void rollext_renderer::render_texture_scan(int32_t scanline, const extent_t &extent, const rollext_polydata &extradata, int threadid)
{
float u = extent.param[0].start;
float v = extent.param[1].start;
float du = extent.param[0].dpdx;
float dv = extent.param[1].dpdx;
uint32_t *fb = &m_fb->pix32(scanline);
uint32_t texbot = extradata.tex_bottom;
uint32_t texleft = extradata.tex_left;
int palnum = extradata.pal;
for (int x = extent.startx; x < extent.stopx; x++)
{
int iu = (int)(u * 29.0f);
int iv = (int)(v * 29.0f);
uint8_t p = m_texture_ram[((texbot - iv) * 2048) + texleft + iu];
uint16_t texel = m_palette_ram[(palnum * 256) + BYTE_XOR_BE(p)];
int r = ((texel >> 10) & 0x1f) << 3;
int g = ((texel >> 5) & 0x1f) << 3;
int b = (texel & 0x1f) << 3;
fb[x] = 0xff000000 | (r << 16) | (g << 8) | b;
u += du;
v += dv;
}
}
/***************************************************************************
World Rally (c) 1993 Gaelco (Designed & Developed by Zigurat. Produced by Gaelco)
Driver by Manuel Abadia, Mike Coates, Nicola Salmoria and Miguel Angel Horna
Thanks to GAELCO SA for the DS5002FP code and information about the encryption
Main PCB components:
====================
CPUs related:
=============
* 1xDS5002FP @ D12 (Dallas security processor @ 12 MHz)
* 1xHM62256ALFP-8T (32KB NVSRAM) @ C11 (encrypted DS5002FP program code)
* 1xLithium cell
* 2xMS6264A-20NC (16KB SRAM) @ D14 & D15 (shared memory between M68000 & DS5002FP)
* 4x74LS157 (Quad 2 input multiplexer) @ F14, F15, F16 & F17 (used to select M68000 or DS5002FP address bus)
* 4x74LS245 (Octal bus transceiver) @ C14, C15, C16 & C17 (used to store shared RAM data)
* 2x74LS373 (Octal tristate latch) @ D16 & D17 (used by DS5002FP to access data from shared RAM)
* 1xMC68000P12 @ C20 (Motorola 68000 @ 12 MHz)
* 1xOSC24MHz @ B20
* 2xM27C4001 @ C22 & C23 (M68000 program ROMs)
* 1xPAL20L8 @ B23 (handles 1st level M68000 memory map)
0 -> DTACK M68000 data ack
1 -> SELACT
2 -> Input/sound (see below)
3 -> ACTEXT
4 -> SELMOV
5 -> CSW
6 -> CSR
7 -> EXT
* 1x74LS138 (3 to 8 line decoder) @ B13 (handles 2nd level M68000 memory map)
0 -> IN0 DIPSW #1 & #2
1 -> IN1 Joystick 1P & 2P, COINSW, STARTSW
2 -> IN2 Wheel input
3 -> -
4 -> IN4 TESTSW & SERVICESW
5 -> OUT (see below)
6 -> CSBAN OKIM6295 bankswitch
7 -> CSSON OKIM6295 R/W
* 1x74LS259 (8 bit addressable latches) @A7 (handles 3rd level M68000 memory map)
0 -> Coin lockout 1
1 -> Coin lockout 2
2 -> Coin counter 1
3 -> Coin counter 2
4 -> Sound muting
5 -> flip screen
6 -> ENA/D?
7 -> CKA/D?
* 1x16AS @ B15
0 -> OE
1 -> XSRL Shared RAM @ D14
2 -> XSRH Shared RAM @ D15
3 -> SAD Shared Access with DS5002FP
4 -> SRE Shared Access with M68000
5 -> TRANS
6 -> XLD
7 -> XHI
Sound related:
==============
* 1xOKIM6295 @ C6
* 1xOSC1MHz @ C7
* 2xM27C4001 @ C1 & C3 (OKI ADPCM samples)
* 1xPAL16R4 @ E2 (handles OKI ROM banking)
Graphics related:
=================
* 1xOSC30MHz @ D5
* 2xTPC1020AFN-84C (FPGA) @ G8 & G13 (GFX processing)
* 2xMS6264A-20NC (8KB SRAM) @ I16 & I17 (Video RAM)
* 4xUM6116BK-25 (2KB SRAM) @ H1, H2, H4 & H5
* 2xUM6116BK-25 (2KB SRAM) @ H22 & H23
Palette related:
================
* 2xMS6264A-20NC (8KB SRAM) @ C8 & C9 (palette RAM (xxxxBBBBRRRRGGGG))
* 2x74HCT273 (octal D-Type flip-flop with clear) @ B8 & B9 (connected to RGB output)
Controls related: (added by Mirko Mattioli)
=================
When optical wheel is selected (via dipswitch), then gear shift (low/high) is enabled.
On the real PCB the optical wheel encoder is connected to 74LS169 ICs (@A16 and @A17)
via a flip-flop IC mounted in the steering wheel assembly. As a result, the output
of the flip-flop generates a signal that contains the information about the steering
direction; this signal is routed to pin #1 (U/D) at ICs A16 and A17 (high when turn
left and low when turn right). The second signal of the optical encoder goes directly
to pin #2 (CLK) at ICs A16 and A17 and it is a clock for the 74LS169 ICs; this clock
frequency is proportional to the movements of the steering wheel: fast movements
produces a high clock frequency, slow movements a low freq.
PCB: REF.930217
The PCB has a layout that can either use the 4 rom set of I7, I9, I11 & I 13 or larger
roms at H8 & H12 for graphics as well as the ability to use different size sound sample
roms at C1 & C3
***************************************************************************/
#include "emu.h"
#include "cpu/m68000/m68000.h"
#include "cpu/mcs51/mcs51.h"
#include "sound/okim6295.h"
#include "includes/wrally.h"
static ADDRESS_MAP_START( wrally_map, AS_PROGRAM, 16, wrally_state )
AM_RANGE(0x000000, 0x0fffff) AM_ROM /* ROM */
AM_RANGE(0x100000, 0x103fff) AM_RAM_WRITE(vram_w) AM_SHARE("videoram") /* encrypted Video RAM */
AM_RANGE(0x108000, 0x108007) AM_RAM AM_SHARE("vregs") /* Video Registers */
AM_RANGE(0x10800c, 0x10800d) AM_WRITENOP /* CLR INT Video */
AM_RANGE(0x200000, 0x203fff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette") /* Palette */
AM_RANGE(0x440000, 0x440fff) AM_RAM AM_SHARE("spriteram") /* Sprite RAM */
AM_RANGE(0x700000, 0x700001) AM_READ_PORT("DSW")
AM_RANGE(0x700002, 0x700003) AM_READ_PORT("P1_P2")
AM_RANGE(0x700004, 0x700005) AM_READ_PORT("WHEEL")
AM_RANGE(0x700008, 0x700009) AM_READ_PORT("SYSTEM")
AM_RANGE(0x70000c, 0x70000d) AM_WRITE(okim6295_bankswitch_w) /* OKI6295 bankswitch */
AM_RANGE(0x70000e, 0x70000f) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff) /* OKI6295 status/data register */
AM_RANGE(0x70000a, 0x70001b) AM_WRITE(wrally_coin_lockout_w) /* Coin lockouts */
AM_RANGE(0x70002a, 0x70003b) AM_WRITE(wrally_coin_counter_w) /* Coin counters */
AM_RANGE(0x70004a, 0x70004b) AM_WRITENOP /* Sound muting */
AM_RANGE(0x70005a, 0x70005b) AM_WRITE(flipscreen_w) /* Flip screen */
AM_RANGE(0x70006a, 0x70007b) AM_WRITENOP /* ??? */
AM_RANGE(0xfec000, 0xfeffff) AM_RAM AM_SHARE("shareram") /* Work RAM (shared with DS5002FP) */
ADDRESS_MAP_END
READ8_MEMBER(wrally_state::dallas_share_r)
{
UINT8 *shareram = (UINT8 *)m_shareram.target();
return shareram[BYTE_XOR_BE(offset)];
}
INLINE void bitmap_4_draw(INT32 firstpix, INT32 iwidth, UINT32 *src, INT32 xpos, UINT8 flags, INT32 dxpos)
{
if (firstpix & 7)
{
UINT32 pixsrc = src[firstpix / 8];
while (firstpix & 7)
{
int pix = (pixsrc >> (4 * (~firstpix & 7))) & 0x0f;
if ((!(flags & 4) || pix) && (UINT32)xpos < 360)
{
if (!(flags & 2))
scanline[xpos] = clutbase[BYTE_XOR_BE(pix)];
else
BLEND(scanline[xpos], clutbase[BYTE_XOR_BE(pix)]);
}
xpos += dxpos;
firstpix++;
}
}
inline void jaguar_state::bitmap_4_draw(UINT16 *scanline, INT32 firstpix, INT32 iwidth, UINT32 *src, INT32 xpos, UINT8 flags, INT32 dxpos, UINT16 *clutbase)
{
if (firstpix & 7)
{
UINT32 pixsrc = src[firstpix >> 3];
while (firstpix & 7)
{
int pix = (pixsrc >> ((~firstpix & 7) << 2)) & 0x0f;
if ((!(flags & 4) || pix) && (UINT32)xpos < 760)
{
if (!(flags & 2))
scanline[xpos] = clutbase[BYTE_XOR_BE(pix)];
else
BLEND(scanline[xpos], clutbase[BYTE_XOR_BE(pix)]);
}
xpos += dxpos;
firstpix++;
}
}
static MC6845_UPDATE_ROW( update_row )
{
tapatune_state *state = device->machine().driver_data<tapatune_state>();
UINT32 *dest = &bitmap.pix32(y);
UINT16 x;
pen_t *pens = (pen_t *)param;
offs_t offs = (ma*2 + ra*0x40)*4;
UINT8 *videoram = reinterpret_cast<UINT8 *>(state->m_videoram.target());
for (x = 0; x < x_count*4; x++)
{
UINT8 pix = videoram[BYTE_XOR_BE(offs + x)];
dest[2*x] = pens[((pix >> 4) & 0x0f)];
dest[2*x + 1] = pens[(pix & 0x0f)];
}
}
static WRITE32_HANDLER( flash_w )
{
static INT32 first_offset = -1;
if(flash_cmd == 0x20200000)
{
// erase game settings
if(data == 0xd0d00000)
{
// point to game settings
UINT8 *rom = (UINT8 *)memory_region(REGION_USER1) + offset*4;
// erase one block
memset(rom, 0xff, 0x10000);
flash_cmd = 0;
}
}
else if(flash_cmd == 0x0f0f0000)
{
if(data == 0xd0d00000 && offset == first_offset)
{
// finished
flash_cmd = 0;
first_offset = -1;
}
else
{
UINT16 *rom = (UINT16 *)memory_region(REGION_USER1);
// write game settings
if(ACCESSING_LSW32)
rom[BYTE_XOR_BE(offset*2 + 1)] = data & 0xffff;
else
rom[BYTE_XOR_BE(offset*2 + 0)] = (data & 0xffff0000) >> 16;
}
}
else
{
static WRITE32_HANDLER( flash_w )
{
dgpix_state *state = space->machine().driver_data<dgpix_state>();
if(state->m_flash_cmd == 0x20200000)
{
// erase game settings
if(data == 0xd0d00000)
{
// point to game settings
UINT8 *rom = (UINT8 *)space->machine().region("user1")->base() + offset*4;
// erase one block
memset(rom, 0xff, 0x10000);
state->m_flash_cmd = 0;
}
}
else if(state->m_flash_cmd == 0x0f0f0000)
{
if(data == 0xd0d00000 && offset == state->m_first_offset)
{
// finished
state->m_flash_cmd = 0;
state->m_first_offset = -1;
}
else
{
UINT16 *rom = (UINT16 *)space->machine().region("user1")->base();
// write game settings
if(ACCESSING_BITS_0_15)
rom[BYTE_XOR_BE(offset*2 + 1)] = data & 0xffff;
else
rom[BYTE_XOR_BE(offset*2 + 0)] = (data & 0xffff0000) >> 16;
}
}
else
{
uint32_t rollext_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
{
#if 0
uint16_t *pal = (uint16_t*)&m_palette_ram[0];
int palnum = 31;
// 24,25,31 for basic font
// 29 = trees
int ii=0;
for (int j=0; j < 384; j++)
{
uint32_t *fb = &bitmap.pix32(j);
for (int i=0; i < 512; i++)
{
uint8_t p = m_texture[ii++];
uint16_t rgb = pal[(palnum * 256) + BYTE_XOR_BE(p)];
int r = ((rgb >> 10) & 0x1f) << 3;
int g = ((rgb >> 5) & 0x1f) << 3;
int b = (rgb & 0x1f) << 3;
fb[i] = 0xff000000 | (r << 16) | (g << 8) | b;
}
ii += 1536;
}
#endif
m_renderer->display(&bitmap, cliprect);
//m_renderer->clear_fb();
//m_disp_ram[0xffffc/4] = 0;
return 0;
}
MACHINE_RESET_MEMBER(gaelco3d_state,gaelco3d2)
{
MACHINE_RESET_CALL_MEMBER( common );
m_tms_offset_xor = BYTE_XOR_BE(0);
}
void memory_array::write8_to_16be(int index, UINT32 data) { reinterpret_cast<UINT8 *>(m_base)[BYTE_XOR_BE(index)] = data; }
UINT32 memory_array::read8_from_16be(int index) { return reinterpret_cast<UINT8 *>(m_base)[BYTE_XOR_BE(index)]; }
static MACHINE_RESET( gaelco3d2 )
{
gaelco3d_state *state = machine.driver_data<gaelco3d_state>();
MACHINE_RESET_CALL( common );
state->m_tms_offset_xor = BYTE_XOR_BE(0);
}
offs_t activecpu_dasm(char *buffer, offs_t pc)
{
VERIFY_ACTIVECPU(activecpu_dasm);
/* allow overrides */
if (cpu_dasm_override)
{
offs_t result = cpu_dasm_override(activecpu, buffer, pc);
if (result)
return result;
}
/* if there's no old-style assembler, do some work to make this call work with the new one */
if (!cpu[activecpu].intf.disassemble)
{
int dbwidth = activecpu_databus_width(ADDRESS_SPACE_PROGRAM);
int maxbytes = activecpu_max_instruction_bytes();
int endianness = activecpu_endianness();
UINT8 opbuf[64], argbuf[64];
int xorval = 0;
int numbytes;
/* determine the XOR to get the bytes in order */
switch (dbwidth)
{
case 8: xorval = 0; break;
case 16: xorval = (endianness == CPU_IS_LE) ? BYTE_XOR_LE(0) : BYTE_XOR_BE(0); break;
case 32: xorval = (endianness == CPU_IS_LE) ? BYTE4_XOR_LE(0) : BYTE4_XOR_BE(0); break;
case 64: xorval = (endianness == CPU_IS_LE) ? BYTE8_XOR_LE(0) : BYTE8_XOR_BE(0); break;
}
/* fetch the bytes up to the maximum */
memset(opbuf, 0xff, sizeof(opbuf));
memset(argbuf, 0xff, sizeof(argbuf));
for (numbytes = 0; numbytes < maxbytes; numbytes++)
{
offs_t physpc = pc + numbytes;
const UINT8 *ptr;
/* translate the address, set the opcode base, and apply the byte xor */
if (!cpu[activecpu].intf.translate || (*cpu[activecpu].intf.translate)(ADDRESS_SPACE_PROGRAM, &physpc))
{
memory_set_opbase(physpc);
physpc ^= xorval;
/* get pointer to data */
ptr = memory_get_op_ptr(cpu_getactivecpu(), physpc, 0);
if (ptr)
{
opbuf[numbytes] = *ptr;
ptr = memory_get_op_ptr(cpu_getactivecpu(), physpc, 1);
if (ptr)
argbuf[numbytes] = *ptr;
else
argbuf[numbytes] = opbuf[numbytes];
}
}
}
return activecpu_dasm_new(buffer, pc, opbuf, argbuf, maxbytes);
}
return (*cpu[activecpu].intf.disassemble)(buffer, pc);
}