static void xgene_enet_cle_bypass(struct xgene_enet_pdata *p, u32 dst_ring_num, u16 bufpool_id) { u32 data, fpsel; data = CFG_CLE_BYPASS_EN0; xgene_enet_wr_csr(p, CLE_BYPASS_REG0_0_ADDR, data); fpsel = xgene_enet_ring_bufnum(bufpool_id) - 0x20; data = CFG_CLE_DSTQID0(dst_ring_num) | CFG_CLE_FPSEL0(fpsel); xgene_enet_wr_csr(p, CLE_BYPASS_REG1_0_ADDR, data); }
static void xgene_enet_cle_bypass(struct xgene_enet_pdata *p, u32 dst_ring_num, u16 bufpool_id) { u32 data, fpsel; u32 cle_bypass_reg0, cle_bypass_reg1; u32 offset = p->port_id * MAC_OFFSET; if (p->enet_id == XGENE_ENET1) { cle_bypass_reg0 = CLE_BYPASS_REG0_0_ADDR; cle_bypass_reg1 = CLE_BYPASS_REG1_0_ADDR; } else { cle_bypass_reg0 = XCLE_BYPASS_REG0_ADDR; cle_bypass_reg1 = XCLE_BYPASS_REG1_ADDR; } data = CFG_CLE_BYPASS_EN0; xgene_enet_wr_csr(p, cle_bypass_reg0 + offset, data); fpsel = xgene_enet_ring_bufnum(bufpool_id) - 0x20; data = CFG_CLE_DSTQID0(dst_ring_num) | CFG_CLE_FPSEL0(fpsel); xgene_enet_wr_csr(p, cle_bypass_reg1 + offset, data); }