static void xgene_enet_xgcle_bypass(struct xgene_enet_pdata *pdata, u32 dst_ring_num, u16 bufpool_id) { u32 cb, fpsel; xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG0_ADDR, &cb); cb |= CFG_CLE_BYPASS_EN0; CFG_CLE_IP_PROTOCOL0_SET(&cb, 3); xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG0_ADDR, cb); fpsel = xgene_enet_ring_bufnum(bufpool_id) - 0x20; xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG1_ADDR, &cb); CFG_CLE_DSTQID0_SET(&cb, dst_ring_num); CFG_CLE_FPSEL0_SET(&cb, fpsel); xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG1_ADDR, cb); }
static void xgene_enet_cle_bypass_mode_cfg(struct xgene_enet_priv *priv, u32 cle_dstqid, u32 cle_fpsel) { u32 reg; xgene_enet_rd(priv, BLOCK_ETH_CSR, CLE_BYPASS_REG0_0_ADDR, ®); reg = CFG_CLE_BYPASS_EN0_SET(reg, 1); reg = CFG_CLE_IP_PROTOCOL0_SET(reg, 3); xgene_enet_wr(priv, BLOCK_ETH_CSR, CLE_BYPASS_REG0_0_ADDR, reg); xgene_enet_rd(priv, BLOCK_ETH_CSR, CLE_BYPASS_REG1_0_ADDR, ®); reg = CFG_CLE_DSTQID0_SET(reg, cle_dstqid); reg = CFG_CLE_FPSEL0_SET(reg, cle_fpsel); xgene_enet_wr(priv, BLOCK_ETH_CSR, CLE_BYPASS_REG1_0_ADDR, reg); xgene_enet_rd(priv, BLOCK_ETH_CSR, CLE_BYPASS_REG8_0_ADDR, ®); reg = CFG_CLE_HENQNUM0_SET(reg, cle_dstqid); xgene_enet_wr(priv, BLOCK_ETH_CSR, CLE_BYPASS_REG8_0_ADDR, reg); }