_ramfunc uint32_t CGU_Init(void) { __disable_irq(); MemoryPinInit(); // Make sure EMC is in high-speed pin mode /* Set the XTAL oscillator frequency to 12MHz*/ CGU_SetXTALOSC(12000000); CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE); CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_SPIFI); CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_M3); /* Set PL160M 12*1 = 12 MHz */ CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1); CGU_SetPLL1(1); CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE); /* Run SPIFI from PL160M, /2 */ CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_CLKSRC_IDIVA); CGU_EnableEntity(CGU_CLKSRC_IDIVA, ENABLE); CGU_SetDIV(CGU_CLKSRC_IDIVA, 2); // This gets adjusted in spi_flash.c to slow the clock when writing CGU_EntityConnect(CGU_CLKSRC_IDIVA, CGU_BASE_SPIFI); CGU_UpdateClock(); LPC_CCU1->CLK_M3_EMCDIV_CFG |= (1<<0) | (1<<5); // Turn on clock / 2 LPC_CREG->CREG6 |= (1<<16); // EMC divided by 2 LPC_CCU1->CLK_M3_EMC_CFG |= (1<<0); // Turn on clock /* Set PL160M @ 12*9=108 MHz */ CGU_SetPLL1(9); /* Run base M3 clock from PL160M, no division */ CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M3); emc_WaitMS(30); /* Change the clock to 180 MHz */ /* Set PL160M @ 12*15=180 MHz */ CGU_SetPLL1(15); emc_WaitMS(30); CGU_UpdateClock(); emc_WaitMS(10); __enable_irq(); return 0; }
/*********************************************************************//** * @brief Initialize default clock for LPC1800 Eval board * @param[in] None * @return Initialize status, could be: * - CGU_ERROR_SUCCESS: successful * - Other: error **********************************************************************/ uint32_t CGU_Init(void){ CGU_SetXTALOSC(12000000); CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE); CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1); // Disable PLL1 CPU hang??? //CGU_EnableEntity(CGU_CLKSRC_PLL1, DISABLE); CGU_SetPLL1(6); CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE); CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M3); CGU_UpdateClock(); return 0; }
/*********************************************************************//** * @brief Initialize default clock for LPC4300 Eval board * @param[in] None * @return Initialize status, could be: * - CGU_ERROR_SUCCESS: successful * - Other: error **********************************************************************/ uint32_t CGU_Init(uint32_t wantedFreq) { uint32_t msel = 0; uint32_t nsel = 0; uint32_t tmp; // Setup PLL1 to 204MHz // 0. Select IRC as BASE_M4_CLK source CGU_EntityConnect(CGU_CLKSRC_IRC, CGU_BASE_M4); SystemCoreClock = 96000000; // 1. Enable the crystal oscillator CGU_SetXTALOSC(12000000); CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE); // 2. Wait 250us cgu_WaitUS(250); // 3. Reconfigure PLL1 as follows: // - Select the M and N divider values to produce the final desired // PLL1 output frequency (204MHz => M=17,N=1 => msel=16,nsel=0) // - Select the crystal oscillator as clock source for PLL1 cgu_findMN(wantedFreq, &msel, &nsel); tmp = LPC_CGU->PLL1_CTRL & ~((0xFF<<16) | (0x03<<12)); LPC_CGU->PLL1_CTRL = tmp | (msel<<16) | (nsel<<12); CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1); // 4. Wait for the PLL1 to lock while((LPC_CGU->PLL1_STAT&1) == 0x0); // 5. Set PLL1 P-divider to divide by 2 (DIRECT=0 and PSEL=0) LPC_CGU->PLL1_CTRL &= ~( (0x03<<8) | CGU_PLL1_DIRECT_MASK ); // 6. Select PLL1 as BASE_M4_CLK source. The BASE_M4_CLK now operates at // the mid frequency range CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M4); SystemCoreClock = (12000000 * (msel+1))/((nsel+1) * 2); // 7. Wait 20us cgu_WaitUS(20); // 8. Set PLL P-divider to direct output mode (DIRECT=1) LPC_CGU->PLL1_CTRL |= CGU_PLL1_DIRECT_MASK; // The BASE_M4_CLK now operates in the high frequency range CGU_UpdateClock(); SystemCoreClock = (12000000 * (msel+1))/(nsel+1); return 0; }
/*********************************************************************//** * @brief Initialize default clock for LPC4300 Eval board * @param[in] None * @return Initialize status, could be: * - CGU_ERROR_SUCCESS: successful * - Other: error **********************************************************************/ uint32_t CGU_Init(void){ CGU_SetXTALOSC(12000000); CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE); CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_M4); CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1); CGU_SetPLL1(6); CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE); CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M4); CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_UART3); CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_UART0); CGU_UpdateClock(); return 0; }
void clockInit(void) { //uint32_t EMCClk; __disable_irq(); /* Set the XTAL oscillator frequency to 12MHz*/ CGU_SetXTALOSC(__CRYSTAL); CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE); CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_M3); /* Set PL160M 12*1 = 12 MHz */ CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1); // CGU_EntityConnect(CGU_CLKSRC_IRC, CGU_CLKSRC_PLL1); CGU_SetPLL1(1); CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE); // setup CLKOUT CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_CLKSRC_IDIVB); CGU_EnableEntity(CGU_CLKSRC_IDIVB, ENABLE); CGU_SetDIV(CGU_CLKSRC_IDIVB, 12); // 12 -> 6 pclks per cpu clk, 10 -> 5 pclks // set input for CLKOUT to IDIVB LPC_CGU->BASE_OUT_CLK &= ~0x0f000000; LPC_CGU->BASE_OUT_CLK |= 0x0d000000; /* Run SPIFI from PL160M, /2 */ CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_CLKSRC_IDIVA); CGU_EnableEntity(CGU_CLKSRC_IDIVA, ENABLE); CGU_SetDIV(CGU_CLKSRC_IDIVA, 2); CGU_EntityConnect(CGU_CLKSRC_IDIVA, CGU_BASE_SPIFI); CGU_UpdateClock(); LPC_CCU1->CLK_M4_EMCDIV_CFG |= (1<<0) | (1<<5); // Turn on clock / 2 LPC_CREG->CREG6 |= (1<<16); // EMC divided by 2 LPC_CCU1->CLK_M4_EMC_CFG |= (1<<0); // Turn on clock /* Set PL160M @ 12*9=108 MHz */ CGU_SetPLL1(9); /* Run base M3 clock from PL160M, no division */ CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M3); waitMS(10); /* Change the clock to 204 MHz */ /* Set PL160M @ 12*15=180 MHz */ CGU_SetPLL1(17); waitMS(10); CGU_UpdateClock(); //EMCFlashInit(); //vEMC_InitSRDRAM(SDRAM_BASE_ADDR, SDRAM_WIDTH, SDRAM_SIZE_MBITS, SDRAM_DATA_BUS_BITS, SDRAM_COL_ADDR_BITS); LPC_SCU->SFSP3_3 = 0xF3; /* high drive for SCLK */ /* IO pins */ LPC_SCU->SFSP3_4=LPC_SCU->SFSP3_5=LPC_SCU->SFSP3_6=LPC_SCU->SFSP3_7 = 0xD3; LPC_SCU->SFSP3_8 = 0x13; /* CS doesn't need feedback */ #if 0 EMCClk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_M3CORE)/2; if (spifi_init(&sobj, 9, S_RCVCLK | S_FULLCLK, EMCClk)) { if (spifi_init(&sobj, 9, S_RCVCLK | S_FULLCLK, EMCClk)) { while(1); } } #endif __enable_irq(); // SPIFI_Init(); }
/********************************************************************** ** Function name: ** ** Description: ** ** Parameters: ** ** Returned value: **********************************************************************/ void Hid_init (void) { USBD_API_INIT_PARAM_T usb_param; USB_CORE_DESCS_T desc; ErrorCode_t ret; USB_INTERFACE_DESCRIPTOR* pIntfDesc; volatile uint32_t CoreM4Freq; // SystemInit(); // CGU_Init(); CoreM4Freq = CGU_GetPCLKFrequency(CGU_PERIPHERAL_M3CORE); /* Disable PLL first */ CGU_EnableEntity(CGU_CLKSRC_PLL0, DISABLE); /* the usb core require output clock = 480MHz */ if(CGU_SetPLL0() != CGU_ERROR_SUCCESS) while(1); CGU_EntityConnect(CGU_CLKSRC_PLL0, CGU_CLKSRC_PLL0); /* Enable PLL after all setting is done */ CGU_EnableEntity(CGU_CLKSRC_PLL0, ENABLE); /* Re-Update the clock freq */ CGU_UpdateClock(); /* Distribute to USB0 base clock */ CGU_EntityConnect(CGU_CLKSRC_PLL0, CGU_BASE_USB0); /* Generate interrupt @ 1000 Hz */ // SysTick_Config(CGU_GetPCLKFrequency(CGU_PERIPHERAL_M3CORE)/1000); /* initilize call back structures */ memset((void*)&usb_param, 0, sizeof(USBD_API_INIT_PARAM_T)); usb_param.usb_reg_base = LPC_USB0_BASE; usb_param.max_num_ep = 6; usb_param.mem_base = 0x20004000; usb_param.mem_size = 0x2000; usb_param.USB_Configure_Event1 = USB_Configure_Event1; /* for eagle/raptor the local SRAM is not accesable to USB * so copy the descriptors to USB accessable memory */ copy_descriptors(&desc, usb_param.mem_base + usb_param.mem_size); /* Turn on the phy */ LPC_CREG->CREG0 &= ~(1<<5); /* USB Initialization */ ret = USBD_API->hw->Init(&hUsb, &desc, &usb_param); if (ret == LPC_OK) { pIntfDesc = (USB_INTERFACE_DESCRIPTOR*)((uint32_t)desc.high_speed_desc + USB_CONFIGUARTION_DESC_SIZE); ret = usb_hid_init(hUsb, pIntfDesc, &usb_param.mem_base, &usb_param.mem_size); if (ret != LPC_OK) vCatchError(0); //"usb_hid_init error!!!" if (ret == LPC_OK) { NVIC_EnableIRQ(USB0_IRQn); // enable USB0 interrrupts /* now connect */ USBD_API->hw->Connect(hUsb, 1); } } else { vCatchError(1); //"\r\nhwUSB_Init error!!!" } #if 0 while (1) { u32Milliseconds = 100; /* Wait... */ while(u32Milliseconds); } #endif }