static void bnx2x_hw_stats_post(struct bnx2x *bp) { struct dmae_command *dmae = &bp->stats_dmae; u32 *stats_comp = bnx2x_sp(bp, stats_comp); *stats_comp = DMAE_COMP_VAL; if (CHIP_REV_IS_SLOW(bp)) return; /* loader */ if (bp->executer_idx) { int loader_idx = PMF_DMAE_C(bp); u32 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC, true, DMAE_COMP_GRC); opcode = bnx2x_dmae_opcode_clr_src_reset(opcode); memset(dmae, 0, sizeof(struct dmae_command)); dmae->opcode = opcode; dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0])); dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0])); dmae->dst_addr_lo = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * (loader_idx + 1)) >> 2; dmae->dst_addr_hi = 0; dmae->len = sizeof(struct dmae_command) >> 2; if (CHIP_IS_E1(bp)) dmae->len--; dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2; dmae->comp_addr_hi = 0; dmae->comp_val = 1; *stats_comp = 0; bnx2x_post_dmae(bp, dmae, loader_idx); } else if (bp->func_stx) {
static enum _ecore_status_t ecore_init_array_dmae(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 addr, u32 dmae_data_offset, u32 size, const u32 *p_buf, bool b_must_dmae, bool b_can_dmae) { enum _ecore_status_t rc = ECORE_SUCCESS; /* Perform DMAE only for lengthy enough sections or for wide-bus */ #ifndef ASIC_ONLY if ((CHIP_REV_IS_SLOW(p_hwfn->p_dev) && (size < 16)) || !b_can_dmae || (!b_must_dmae && (size < 16))) { #else if (!b_can_dmae || (!b_must_dmae && (size < 16))) { #endif const u32 *data = p_buf + dmae_data_offset; u32 i; for (i = 0; i < size; i++) ecore_wr(p_hwfn, p_ptt, addr + (i << 2), data[i]); } else { rc = ecore_dmae_host2grc(p_hwfn, p_ptt, (osal_uintptr_t)(p_buf + dmae_data_offset), addr, size, OSAL_NULL /* default parameters */); } return rc; } static enum _ecore_status_t ecore_init_fill_dmae(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 addr, u32 fill_count) { static u32 zero_buffer[DMAE_MAX_RW_SIZE]; struct ecore_dmae_params params; OSAL_MEMSET(zero_buffer, 0, sizeof(u32) * DMAE_MAX_RW_SIZE); OSAL_MEMSET(¶ms, 0, sizeof(params)); params.flags = ECORE_DMAE_FLAG_RW_REPL_SRC; return ecore_dmae_host2grc(p_hwfn, p_ptt, (osal_uintptr_t)(&(zero_buffer[0])), addr, fill_count, ¶ms); } static void ecore_init_fill(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 addr, u32 fill, u32 fill_count) { u32 i; for (i = 0; i < fill_count; i++, addr += sizeof(u32)) ecore_wr(p_hwfn, p_ptt, addr, fill); }
void ecore_gtt_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) { u32 gtt_base; u32 i; #ifndef ASIC_ONLY if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { /* This is done by MFW on ASIC; regardless, this should only * be done once per chip [i.e., common]. Implementation is * not too bright, but it should work on the simple FPGA/EMUL * scenarios. */ static bool initialized = false; int poll_cnt = 500; u32 val; /* initialize PTT/GTT (poll for completion) */ if (!initialized) { ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_START_INIT_PTT_GTT, 1); initialized = true; } do { /* ptt might be overrided by HW until this is done */ OSAL_UDELAY(10); ecore_ptt_invalidate(p_hwfn); val = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_INIT_DONE_PTT_GTT); } while ((val != 1) && --poll_cnt); if (!poll_cnt) DP_ERR(p_hwfn, "PGLUE_B_REG_INIT_DONE didn't complete\n"); } #endif /* Set the global windows */ gtt_base = PXP_PF_WINDOW_ADMIN_START + PXP_PF_WINDOW_ADMIN_GLOBAL_START; for (i = 0; i < OSAL_ARRAY_SIZE(pxp_global_win); i++) if (pxp_global_win[i]) REG_WR(p_hwfn, gtt_base + i * PXP_GLOBAL_ENTRY_SIZE, pxp_global_win[i]); }
static void bnx2x_hw_stats_post(struct bnx2x *bp) { struct dmae_command *dmae = &bp->stats_dmae; u32 *stats_comp = bnx2x_sp(bp, stats_comp); *stats_comp = DMAE_COMP_VAL; if (CHIP_REV_IS_SLOW(bp)) return; /* loader */ if (bp->executer_idx) { int loader_idx = PMF_DMAE_C(bp); memset(dmae, 0, sizeof(struct dmae_command)); dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC | DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE | DMAE_CMD_DST_RESET | #ifdef __BIG_ENDIAN DMAE_CMD_ENDIANITY_B_DW_SWAP | #else DMAE_CMD_ENDIANITY_DW_SWAP | #endif (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) | (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT)); dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0])); dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0])); dmae->dst_addr_lo = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * (loader_idx + 1)) >> 2; dmae->dst_addr_hi = 0; dmae->len = sizeof(struct dmae_command) >> 2; if (CHIP_IS_E1(bp)) dmae->len--; dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2; dmae->comp_addr_hi = 0; dmae->comp_val = 1; *stats_comp = 0; bnx2x_post_dmae(bp, dmae, loader_idx); } else if (bp->func_stx) {