int zynq_clk_init(void)
{
zynq_slcr_unlock();
SLCR_REG(DCI_CLK_CTRL) = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR1(52) | CLK_CTRL_DIVISOR2(2);
SLCR_REG(GEM0_RCLK_CTRL) = CLK_CTRL_CLKACT1;
SLCR_REG(GEM0_CLK_CTRL) = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR1(8) | CLK_CTRL_DIVISOR2(1);
SLCR_REG(LQSPI_CLK_CTRL) = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR1(5);
SLCR_REG(SDIO_CLK_CTRL) = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR1(20);
SLCR_REG(UART_CLK_CTRL) = CLK_CTRL_CLKACT2 | CLK_CTRL_DIVISOR1(20);
SLCR_REG(PCAP_CLK_CTRL) = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR1(5);
SLCR_REG(FPGA0_CLK_CTRL) = CLK_CTRL_DIVISOR1(10) | CLK_CTRL_DIVISOR2(1);
SLCR_REG(FPGA1_CLK_CTRL) = CLK_CTRL_SRCSEL(3) | CLK_CTRL_DIVISOR1(6) | CLK_CTRL_DIVISOR2(1);
SLCR_REG(FPGA2_CLK_CTRL) = CLK_CTRL_SRCSEL(2) | CLK_CTRL_DIVISOR1(53) | CLK_CTRL_DIVISOR2(2);
SLCR_REG(FPGA3_CLK_CTRL) = CLK_CTRL_DIVISOR2(1);
SLCR_REG(CLK_621_TRUE) = CLK_621_ENABLE;
SLCR_REG(APER_CLK_CTRL) = DMA_CPU_CLK_EN | USB0_CPU_CLK_EN | USB1_CPU_CLK_EN |
GEM0_CPU_CLK_EN | SDI0_CPU_CLK_EN | I2C0_CPU_CLK_EN |
I2C1_CPU_CLK_EN | UART1_CPU_CLK_EN | GPIO_CPU_CLK_EN |
LQSPI_CPU_CLK_EN | SMC_CPU_CLK_EN;
zynq_slcr_lock();
return 0;
}
[49] = MIO_TRI_ENABLE | MIO_L3_SEL(0x7) | MIO_IO_TYPE_LVCMOS18,
// 50-51 are BTN4 and BTN5
[50] = MIO_IO_TYPE_LVCMOS18 | MIO_DISABLE_RCVR,
[51] = MIO_IO_TYPE_LVCMOS18 | MIO_DISABLE_RCVR,
// 52-53 gem0
[52] = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18 | MIO_PULLUP,
[53] = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18 | MIO_PULLUP,
};
const zynq_clk_cfg_t zynq_clk_cfg = {
.arm_clk = ARM_CLK_CTRL_DIVISOR(2) | ARM_CLK_CTRL_CPU_6OR4XCLKACT |
ARM_CLK_CTRL_CPU_3OR2XCLKACT | ARM_CLK_CTRL_CPU_2XCLKACT |
ARM_CLK_CTRL_CPU_1XCLKACT |ARM_CLK_CTRL_PERI_CLKACT,
.ddr_clk = DDR_CLK_CTRL_DDR_3XCLKACT | DDR_CLK_CTRL_DDR_2XCLKACT |
DDR_CLK_CTRL_DDR_3XCLK_DIV(2) | DDR_CLK_CTRL_DDR_2XCLK_DIV(3),
.dci_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(52) | CLK_CTRL_DIVISOR1(2),
.gem0_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(8) | CLK_CTRL_DIVISOR1(1),
.gem0_rclk = CLK_CTRL_CLKACT,
.lqspi_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(5),
.sdio_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(20),
.uart_clk = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR0(20),
.pcap_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(5),
.fpga0_clk = CLK_CTRL_DIVISOR0(10) | CLK_CTRL_DIVISOR1(1),
.fpga1_clk = CLK_CTRL_SRCSEL(3) | CLK_CTRL_DIVISOR0(6) | CLK_CTRL_DIVISOR1(1),
.fpga2_clk = CLK_CTRL_SRCSEL(2) | CLK_CTRL_DIVISOR0(53) | CLK_CTRL_DIVISOR1(2),
.fpga3_clk = CLK_CTRL_DIVISOR1(1),
.aper_clk = DMA_CPU_CLK_EN | USB0_CPU_CLK_EN | USB1_CPU_CLK_EN |
GEM0_CPU_CLK_EN | SDI0_CPU_CLK_EN | I2C0_CPU_CLK_EN |
I2C1_CPU_CLK_EN | UART1_CPU_CLK_EN | GPIO_CPU_CLK_EN |
LQSPI_CPU_CLK_EN | SMC_CPU_CLK_EN,
.clk_621_true = CLK_621_ENABLE,
[48] = MIO_L3_SEL(0x7) | MIO_IO_TYPE_LVCMOS18,
[49] = MIO_TRI_ENABLE | MIO_L3_SEL(0x7) | MIO_IO_TYPE_LVCMOS18,
[50] = MIO_TRI_ENABLE | MIO_IO_TYPE_LVCMOS18,
[51] = MIO_IO_TYPE_LVCMOS18,
// 52-53 gem0
[52] = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18 | MIO_PULLUP,
[53] = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18 | MIO_PULLUP,
};
const zynq_clk_cfg_t zynq_clk_cfg = {
.arm_clk = ARM_CLK_CTRL_DIVISOR(2) | ARM_CLK_CTRL_CPU_6OR4XCLKACT |
ARM_CLK_CTRL_CPU_3OR2XCLKACT | ARM_CLK_CTRL_CPU_2XCLKACT |
ARM_CLK_CTRL_CPU_1XCLKACT | ARM_CLK_CTRL_PERI_CLKACT,
.ddr_clk = DDR_CLK_CTRL_DDR_3XCLKACT | DDR_CLK_CTRL_DDR_2XCLKACT |
DDR_CLK_CTRL_DDR_3XCLK_DIV(2) | DDR_CLK_CTRL_DDR_2XCLK_DIV(3),
.dci_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(35) | CLK_CTRL_DIVISOR1(3),
.gem0_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(8) | CLK_CTRL_DIVISOR1(1),
.gem0_rclk = CLK_CTRL_CLKACT,
.lqspi_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(5),
.sdio_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(20),
.uart_clk = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR0(20),
.pcap_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(5),
.fpga0_clk = CLK_CTRL_DIVISOR0(10) | CLK_CTRL_DIVISOR1(1),
.fpga1_clk = CLK_CTRL_DIVISOR0(10) | CLK_CTRL_DIVISOR1(1),
.fpga2_clk = CLK_CTRL_DIVISOR0(30) | CLK_CTRL_DIVISOR1(1),
.fpga3_clk = CLK_CTRL_DIVISOR0(20) | CLK_CTRL_DIVISOR1(1),
.aper_clk = DMA_CPU_CLK_EN | USB0_CPU_CLK_EN | USB1_CPU_CLK_EN | GEM0_CPU_CLK_EN |
SDI0_CPU_CLK_EN | I2C0_CPU_CLK_EN | I2C1_CPU_CLK_EN | UART1_CPU_CLK_EN |
GPIO_CPU_CLK_EN | LQSPI_CPU_CLK_EN | SMC_CPU_CLK_EN,
.clk_621_true = CLK_621_ENABLE,
};
