int zynq_clk_init(void)
{
zynq_slcr_unlock();
SLCR_REG(DCI_CLK_CTRL) = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR1(52) | CLK_CTRL_DIVISOR2(2);
SLCR_REG(GEM0_RCLK_CTRL) = CLK_CTRL_CLKACT1;
SLCR_REG(GEM0_CLK_CTRL) = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR1(8) | CLK_CTRL_DIVISOR2(1);
SLCR_REG(LQSPI_CLK_CTRL) = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR1(5);
SLCR_REG(SDIO_CLK_CTRL) = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR1(20);
SLCR_REG(UART_CLK_CTRL) = CLK_CTRL_CLKACT2 | CLK_CTRL_DIVISOR1(20);
SLCR_REG(PCAP_CLK_CTRL) = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR1(5);
SLCR_REG(FPGA0_CLK_CTRL) = CLK_CTRL_DIVISOR1(10) | CLK_CTRL_DIVISOR2(1);
SLCR_REG(FPGA1_CLK_CTRL) = CLK_CTRL_SRCSEL(3) | CLK_CTRL_DIVISOR1(6) | CLK_CTRL_DIVISOR2(1);
SLCR_REG(FPGA2_CLK_CTRL) = CLK_CTRL_SRCSEL(2) | CLK_CTRL_DIVISOR1(53) | CLK_CTRL_DIVISOR2(2);
SLCR_REG(FPGA3_CLK_CTRL) = CLK_CTRL_DIVISOR2(1);
SLCR_REG(CLK_621_TRUE) = CLK_621_ENABLE;
SLCR_REG(APER_CLK_CTRL) = DMA_CPU_CLK_EN | USB0_CPU_CLK_EN | USB1_CPU_CLK_EN |
GEM0_CPU_CLK_EN | SDI0_CPU_CLK_EN | I2C0_CPU_CLK_EN |
I2C1_CPU_CLK_EN | UART1_CPU_CLK_EN | GPIO_CPU_CLK_EN |
LQSPI_CPU_CLK_EN | SMC_CPU_CLK_EN;
zynq_slcr_lock();
return 0;
}
/**
* Init PLL's for Zynq 7020
*
* @return
*/
static int32_t zynq_InitPll( const Mcu_ClockSettingConfigType *cPtr ) {
SLCR.SLCR_UNLOCK = 0x0000DF0DU; /* Unlock SLCR registers */
READWRITE32((uint32)&SLCR.ARM_PLL_CFG, 0x003FFFF0U , cPtr->ARM_PLL_CFG );
READWRITE32((uint32)&SLCR.ARM_PLL_CTRL, 0x0007F000U , cPtr->ARM_PLL_CTRL);
/* Set PLL_BYPASS_FORCE */
READWRITE32((uint32)&SLCR.ARM_PLL_CTRL, 0x00000010U ,0x00000010U);
/* Assert PLL_RESET */
READWRITE32((uint32)&SLCR.ARM_PLL_CTRL, 0x00000001U ,0x00000001U);
/* De-Assert PLL_RESET */
READWRITE32((uint32)&SLCR.ARM_PLL_CTRL, 0x00000001U ,0x00000000U);
/* Check ARM_PLL_LOCK Status */
while( !(SLCR.PLL_STATUS & 1) ) {}; /* IMPROVEMENT: Add timeout */
READWRITE32((uint32)&SLCR.ARM_PLL_CTRL, 0x00000010U ,0x00000000U);
READWRITE32((uint32)&SLCR.ARM_CLK_CTRL,
0x1F000000U | CLK_CTRL_DIVISOR_M | CLK_CTRL_SRCSEL_M ,
cPtr->ARM_CLK_CTRL | CLK_CTRL_SRCSEL(SRCSEL_ARM_CLK_CTRL_ARM_PLL));
/* IO_PLL Setup */
READWRITE32((uint32)&SLCR.IO_PLL_CFG, 0x003FFFF0U , cPtr->IO_PLL_CFG );
READWRITE32((uint32)&SLCR.IO_PLL_CTRL, 0x0007F000U , cPtr->IO_PLL_CTRL);
READWRITE32((uint32)&SLCR.IO_PLL_CTRL, 0x00000010U ,0x00000010U);
READWRITE32((uint32)&SLCR.IO_PLL_CTRL, 0x00000001U ,0x00000001U);
READWRITE32((uint32)&SLCR.IO_PLL_CTRL, 0x00000001U ,0x00000000U);
while( !(SLCR.PLL_STATUS & 4) ) {}; /* IMPROVEMENT: Add timeout */
READWRITE32((uint32)&SLCR.IO_PLL_CTRL, 0x00000010U ,0x00000000U);
SLCR.SLCR_LOCK = 0x0000767BU; /* Lock SLCR again */
return 0;
}
const zynq_clk_cfg_t zynq_clk_cfg = {
.arm_clk = ARM_CLK_CTRL_DIVISOR(2) | ARM_CLK_CTRL_CPU_6OR4XCLKACT |
ARM_CLK_CTRL_CPU_3OR2XCLKACT | ARM_CLK_CTRL_CPU_2XCLKACT |
ARM_CLK_CTRL_CPU_1XCLKACT |ARM_CLK_CTRL_PERI_CLKACT,
.ddr_clk = DDR_CLK_CTRL_DDR_3XCLKACT | DDR_CLK_CTRL_DDR_2XCLKACT |
DDR_CLK_CTRL_DDR_3XCLK_DIV(2) | DDR_CLK_CTRL_DDR_2XCLK_DIV(3),
.dci_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(52) | CLK_CTRL_DIVISOR1(2),
.gem0_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(8) | CLK_CTRL_DIVISOR1(1),
.gem0_rclk = CLK_CTRL_CLKACT,
.lqspi_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(5),
.sdio_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(20),
.uart_clk = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR0(20),
.pcap_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(5),
.fpga0_clk = CLK_CTRL_DIVISOR0(10) | CLK_CTRL_DIVISOR1(1),
.fpga1_clk = CLK_CTRL_SRCSEL(3) | CLK_CTRL_DIVISOR0(6) | CLK_CTRL_DIVISOR1(1),
.fpga2_clk = CLK_CTRL_SRCSEL(2) | CLK_CTRL_DIVISOR0(53) | CLK_CTRL_DIVISOR1(2),
.fpga3_clk = CLK_CTRL_DIVISOR1(1),
.aper_clk = DMA_CPU_CLK_EN | USB0_CPU_CLK_EN | USB1_CPU_CLK_EN |
GEM0_CPU_CLK_EN | SDI0_CPU_CLK_EN | I2C0_CPU_CLK_EN |
I2C1_CPU_CLK_EN | UART1_CPU_CLK_EN | GPIO_CPU_CLK_EN |
LQSPI_CPU_CLK_EN | SMC_CPU_CLK_EN,
.clk_621_true = CLK_621_ENABLE,
};
void target_early_init(void)
{
gpio_config(GPIO_LEDY, GPIO_OUTPUT);
gpio_set(GPIO_LEDY, 0);
}
/**
* Init clocks
*
* @param cPtr Pointer to the clock settings configuration
* @return
*/
static int32_t zynq_InitClocks( const Mcu_ClockSettingConfigType *cPtr ) {
SLCR.SLCR_UNLOCK = 0x0000DF0DU; /* Unlock SLCR registers */
/* CAN 0 and 1*/
READWRITE32((uint32)&SLCR.CAN_CLK_CTRL,
CLK_CTRL_DIVISOR_M + CLK_CTRL_DIVISOR1_M + CLK_CTRL_SRCSEL_M + 3 ,
cPtr->CAN_CLK_CTRL + CLK_CTRL_SRCSEL(SRCSEL_IO_PLL));
READWRITE32( (uint32)&SLCR.CAN_MIOCLK_CTRL , 0xffffffff , cPtr->CAN_MIOCLK_CTRL);
/* Eth 0 */
READWRITE32((uint32)&SLCR.GEM0_CLK_CTRL,
CLK_CTRL_DIVISOR_M + CLK_CTRL_DIVISOR1_M + CLK_CTRL_SRCSEL_M + 1 ,
cPtr->GEM0_CLK_CTRL + CLK_CTRL_SRCSEL(SRCSEL_IO_PLL));
/* Eth 1 */
READWRITE32((uint32)&SLCR.GEM1_CLK_CTRL,
CLK_CTRL_DIVISOR_M + CLK_CTRL_DIVISOR1_M + CLK_CTRL_SRCSEL_M + 1 ,
cPtr->GEM1_CLK_CTRL + CLK_CTRL_SRCSEL(SRCSEL_IO_PLL));
/* SMC */
READWRITE32((uint32)&SLCR.SMC_CLK_CTRL,
CLK_CTRL_DIVISOR_M + CLK_CTRL_SRCSEL_M + 1 ,
cPtr->SMC_CLK_CTRL + CLK_CTRL_SRCSEL(SRCSEL_IO_PLL));
/* QuadSPI */
READWRITE32((uint32)&SLCR.LQSPI_CLK_CTRL,
CLK_CTRL_DIVISOR_M + CLK_CTRL_SRCSEL_M + 1 ,
cPtr->LQSPI_CLK_CTRL + CLK_CTRL_SRCSEL(SRCSEL_IO_PLL));
/* Skip FPGA clocks for now, ie PllFckDivisor_0 and PllFckDivisor_1 */
/* SDIO 0 and 1 */
READWRITE32((uint32)&SLCR.SDIO_CLK_CTRL,
CLK_CTRL_DIVISOR_M + CLK_CTRL_SRCSEL_M + 3 ,
cPtr->SDIO_CLK_CTRL + CLK_CTRL_SRCSEL(SRCSEL_IO_PLL));
/* Uart 0 and 1 */
READWRITE32((uint32)&SLCR.UART_CLK_CTRL,
CLK_CTRL_DIVISOR_M + CLK_CTRL_SRCSEL_M + 3 ,
cPtr->UART_CLK_CTRL + CLK_CTRL_SRCSEL(SRCSEL_IO_PLL));
/* SPI 0 and 1 */
READWRITE32((uint32)&SLCR.SPI_CLK_CTRL,
CLK_CTRL_DIVISOR_M + CLK_CTRL_SRCSEL_M + 3 ,
cPtr->SPI_CLK_CTRL + CLK_CTRL_SRCSEL(SRCSEL_IO_PLL));
/* Trace, Skip for now */
/* PCAP */
READWRITE32((uint32)&SLCR.PCAP_CLK_CTRL,
CLK_CTRL_DIVISOR_M + CLK_CTRL_SRCSEL_M + 1 ,
cPtr->PCAP_CLK_CTRL + CLK_CTRL_SRCSEL(SRCSEL_IO_PLL));
/* Write APER */
{
uint32 val = ((cPtr->SMC_CLK_CTRL & 1)<<24) +
((cPtr->LQSPI_CLK_CTRL & 1)<<23) +
/* 22 GPIO */
((cPtr->UART_CLK_CTRL & 2)<<20) +
((cPtr->UART_CLK_CTRL & 1)<<20) +
/* 19-18 I2C */
((cPtr->CAN_CLK_CTRL & 2)<<16) +
((cPtr->CAN_CLK_CTRL & 1)<<16) +
((cPtr->SPI_CLK_CTRL & 2)<<14) +
((cPtr->SPI_CLK_CTRL & 1)<<14) +
/* 13,12 reserved */
((cPtr->SDIO_CLK_CTRL & 2)<<10) +
((cPtr->SDIO_CLK_CTRL & 1)<<10) +
/* 9,8 reserved */
((cPtr->GEM0_CLK_CTRL & 1)<<7) +
((cPtr->GEM1_CLK_CTRL & 1)<<6)
/* 1 reserved */
/* 0 DMA */
;
READWRITE32((uint32)&SLCR.APER_CLK_CTRL,
(3<<23)+(3<<20)+(3<<16)+(3<<14)+(3<<10)+(3<<6),
val);
}
SLCR.SLCR_LOCK = 0x0000767BU; /* Lock SLCR again */
return 0;
}
