static void
i2c_init(wm_i2c *i2c)
{
static int clock_inited = 0;
if (!clock_inited) {
CLK_Module_Type clkmod;
switch (i2c->port) {
case 0:
default:
clkmod = CLK_I2C0;
break;
case 1:
clkmod = CLK_I2C1;
break;
case 2:
clkmod = CLK_I2C2;
break;
}
CLK_ModuleClkEnable(clkmod);
CLK_ModuleClkDivider(clkmod, CLK_DIV);
clock_inited = true;
}
i2c_config(i2c);
}
uint32_t ssp_drv_set_clk(SSP_ID_Type ssp_id, uint32_t freq)
{
mdev_t *mdev_p;
sspdev_data_t *ssp_data_p;
uint16_t divider;
if (!IS_SSP_PERIPH(ssp_id) || freq <= 0)
return -WM_FAIL;
/* Check ssp_id is initialized */
mdev_p = mdev_get_handle(mdev_ssp_name[ssp_id]);
if (!mdev_p) {
SSP_LOG("Unable to open device %s\r\n",
mdev_ssp_name[ssp_id]);
return -WM_FAIL;
}
ssp_data_p = (sspdev_data_t *) mdev_p->private_data;
/* Calculate Divider */
divider = (uint32_t)(board_cpu_freq()/freq);
ssp_data_p->freq = (uint32_t)((board_cpu_freq() / divider));
if (!IS_SSP_DIVIDER(divider)) {
SSP_LOG("Unable to set %u frequency for %s %d\r\n",
freq, mdev_ssp_name[ssp_id], divider);
ssp_data_p->freq = 0;
return -WM_FAIL;
}
switch (ssp_id) {
case SSP0_ID:
CLK_ModuleClkEnable(CLK_SSP0);
CLK_SSPClkSrc(CLK_SSP_ID_0, CLK_SYSTEM);
CLK_ModuleClkDivider(CLK_SSP0, divider);
break;
case SSP1_ID:
CLK_ModuleClkEnable(CLK_SSP1);
CLK_SSPClkSrc(CLK_SSP_ID_1, CLK_SYSTEM);
CLK_ModuleClkDivider(CLK_SSP1, divider);
break;
case SSP2_ID:
CLK_ModuleClkEnable(CLK_SSP2);
CLK_SSPClkSrc(CLK_SSP_ID_2, CLK_SYSTEM);
CLK_ModuleClkDivider(CLK_SSP2, divider);
break;
}
return ssp_data_p->freq;
}
void
xs_wdt_start(xsMachine *the)
{
int index = xsToInteger(xsArg(0));
WDT_Config_Type cfg;
cfg.timeoutVal = index;
cfg.mode = WDT_MODE_RESET;
cfg.resetPulseLen = WDT_RESET_PULSE_LEN_2;
WDT_Init(&cfg);
CLK_ModuleClkEnable(CLK_WDT);
#if defined(CONFIG_CPU_MW300)
/* For 88MW300, APB1 bus runs at 50MHz whereas for 88MC200 it runs at
* 25MHz, hence following clk divider is added to keep timeout same.
*/
CLK_ModuleClkDivider(CLK_WDT, 1);
#endif
WDT_Enable();
wdt_enable = 1;
}
