/******************************************************************************* * Code for BOARD_BootClockPLL180M configuration ******************************************************************************/ void BOARD_BootClockPLL180M(void) { /*!< Set up the clock sources */ /*!< Set up FRO */ POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ CLOCK_AttachClk( kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally being below the voltage for current speed */ POWER_SetVoltageForFreq( 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ /*!< Set up SYS PLL */ const pll_setup_t pllSetup = { .pllctrl = SYSCON_SYSPLLCTRL_SELI(32U) | SYSCON_SYSPLLCTRL_SELP(16U) | SYSCON_SYSPLLCTRL_SELR(0U), .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)), .pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)), .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)), .pllRate = 180000000U, .flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP}; CLOCK_AttachClk(kEXT_CLK_to_SYS_PLL); /*!< Set sys pll clock source from external crystal */ CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */ POWER_SetVoltageForFreq( 180000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ CLOCK_SetFLASHAccessCyclesForFreq(180000000U); /*!< Set FLASH wait states for core */ CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch System clock to SYS PLL 180MHz */ /* Set SystemCoreClock variable. */ SystemCoreClock = BOARD_BootClockPLL180M_CORE_CLOCK; }
/******************************************************************************* * Code for BOARD_BootClockFRO12M configuration ******************************************************************************/ void BOARD_BootClockFRO12M(void) { /*!< Set up the clock sources */ /*!< Set up FRO */ POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally being below the voltage for current speed */ CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ /*!< Set up dividers */ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ /*!< Set up clock selectors - Attach clocks to the peripheries */ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ /*!< Set SystemCoreClock variable. */ SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; }
/* Initialize debug console. */ status_t BOARD_InitDebugConsole(void) { status_t result; /* attach 12 MHz clock to FLEXCOMM0 (debug console) */ CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH); RESET_PeripheralReset(BOARD_DEBUG_UART_RST); // result = DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, BOARD_DEBUG_UART_BAUDRATE, DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM, // BOARD_DEBUG_UART_CLK_FREQ); assert(kStatus_Success == result); return result; }
void spi_format(spi_t *obj, int bits, int mode, int slave) { spi_master_config_t master_config; spi_slave_config_t slave_config; /* Bits: values between 4 and 16 are valid */ MBED_ASSERT(bits >= 4 && bits <= 16); obj->bits = bits; if (slave) { /* Slave config */ SPI_SlaveGetDefaultConfig(&slave_config); slave_config.dataWidth = (spi_data_width_t)(bits - 1); slave_config.polarity = (mode & 0x2) ? kSPI_ClockPolarityActiveLow : kSPI_ClockPolarityActiveHigh; slave_config.phase = (mode & 0x1) ? kSPI_ClockPhaseSecondEdge : kSPI_ClockPhaseFirstEdge; SPI_SlaveInit(spi_address[obj->instance], &slave_config); } else { /* Master config */ SPI_MasterGetDefaultConfig(&master_config); master_config.dataWidth = (spi_data_width_t)(bits - 1); master_config.polarity = (mode & 0x2) ? kSPI_ClockPolarityActiveLow : kSPI_ClockPolarityActiveHigh; master_config.phase = (mode & 0x1) ? kSPI_ClockPhaseSecondEdge : kSPI_ClockPhaseFirstEdge; master_config.direction = kSPI_MsbFirst; switch (obj->instance) { case 0: CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0); RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn); break; case 1: CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1); RESET_PeripheralReset(kFC1_RST_SHIFT_RSTn); break; case 2: CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2); RESET_PeripheralReset(kFC2_RST_SHIFT_RSTn); break; case 3: CLOCK_AttachClk(kFRO12M_to_FLEXCOMM3); RESET_PeripheralReset(kFC3_RST_SHIFT_RSTn); break; case 4: CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4); RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn); break; case 5: CLOCK_AttachClk(kFRO12M_to_FLEXCOMM5); RESET_PeripheralReset(kFC5_RST_SHIFT_RSTn); break; case 6: CLOCK_AttachClk(kFRO12M_to_FLEXCOMM6); RESET_PeripheralReset(kFC6_RST_SHIFT_RSTn); break; case 7: CLOCK_AttachClk(kFRO12M_to_FLEXCOMM7); RESET_PeripheralReset(kFC7_RST_SHIFT_RSTn); break; #if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 8U) case 8: CLOCK_AttachClk(kFRO12M_to_FLEXCOMM8); RESET_PeripheralReset(kFC8_RST_SHIFT_RSTn); break; #endif #if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 9U) case 9: CLOCK_AttachClk(kFRO12M_to_FLEXCOMM9); RESET_PeripheralReset(kFC9_RST_SHIFT_RSTn); break; #endif } SPI_MasterInit(spi_address[obj->instance], &master_config, 12000000); } }
/******************************************************************************* * Code for BOARD_BootClockPLL180M configuration ******************************************************************************/ void BOARD_BootClockPLL180M(void) { /*!< Set up the clock sources */ /*!< Set up FRO */ POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ CLOCK_AttachClk( kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally being below the voltage for current speed */ POWER_SetVoltageForFreq( 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ /*!< Set up SYS PLL */ const pll_setup_t pllSetup = { .pllctrl = SYSCON_SYSPLLCTRL_SELI(32U) | SYSCON_SYSPLLCTRL_SELP(16U) | SYSCON_SYSPLLCTRL_SELR(0U), .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)), .pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)), .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)), .pllRate = 180000000U, .flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP}; CLOCK_AttachClk(kEXT_CLK_to_SYS_PLL); /*!< Set sys pll clock source from external crystal */ CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */ POWER_SetVoltageForFreq( 180000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ CLOCK_SetFLASHAccessCyclesForFreq(180000000U); /*!< Set FLASH wait states for core */ CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch System clock to SYS PLL 180MHz */ /* Set SystemCoreClock variable. */ SystemCoreClock = BOARD_BOOTCLOCKPLL180M_CORE_CLOCK; } /******************************************************************************* ******************** Configuration BOARD_BootClockPLL220M ********************* ******************************************************************************/ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!Configuration name: BOARD_BootClockPLL220M called_from_default_init: true outputs: - {id: FRO12M_clock.outFreq, value: 12 MHz} - {id: FROHF_clock.outFreq, value: 48 MHz} - {id: MAIN_clock.outFreq, value: 220 MHz} - {id: SYSPLL_clock.outFreq, value: 220 MHz} - {id: System_clock.outFreq, value: 220 MHz} settings: - {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS} - {id: SYSCON.M_MULT.scale, value: '110', locked: true} - {id: SYSCON.N_DIV.scale, value: '3', locked: true} - {id: SYSCON.PDEC.scale, value: '2', locked: true} - {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /******************************************************************************* * Variables for BOARD_BootClockPLL220M configuration ******************************************************************************/ /******************************************************************************* * Code for BOARD_BootClockPLL220M configuration ******************************************************************************/ void BOARD_BootClockPLL220M(void) { /*!< Set up the clock sources */ /*!< Set up FRO */ POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally being below the voltage for current speed */ POWER_SetVoltageForFreq(220000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ CLOCK_SetFLASHAccessCyclesForFreq(220000000U); /*!< Set FLASH wait states for core */ /*!< Set up SYS PLL */ const pll_setup_t pllSetup = { .pllctrl = SYSCON_SYSPLLCTRL_SELI(34U) | SYSCON_SYSPLLCTRL_SELP(31U) | SYSCON_SYSPLLCTRL_SELR(0U), .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(13243U)), .pllndec = (SYSCON_SYSPLLNDEC_NDEC(1U)), .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)), .pllRate = 220000000U, .flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP }; CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /*!< Set sys pll clock source*/ CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */ /*!< Set up dividers */ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */ /*!< Set up clock selectors - Attach clocks to the peripheries */ CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL */ SYSCON->MAINCLKSELA = ((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) | SYSCON_MAINCLKSELA_SEL(0U)); /*!< Switch MAINCLKSELA to FRO12M even it is not used for MAINCLKSELB */ /* Set SystemCoreClock variable. */ SystemCoreClock = BOARD_BOOTCLOCKPLL220M_CORE_CLOCK; }
/* RT-Thread Device Interface */ static rt_err_t rt_lcd_init(rt_device_t dev) { /* Route Main clock to LCD. */ CLOCK_AttachClk(kMCLK_to_LCD_CLK); CLOCK_SetClkDiv(kCLOCK_DivLcdClk, 1, true); /*LCD管脚配置*/ lcd_gpio_init(); /* Set the back light PWM. */ { sctimer_config_t config; sctimer_pwm_signal_param_t pwmParam; uint32_t event; CLOCK_AttachClk(kMCLK_to_SCT_CLK); CLOCK_SetClkDiv(kCLOCK_DivSctClk, 2, true); SCTIMER_GetDefaultConfig(&config); SCTIMER_Init(SCT0, &config); pwmParam.output = kSCTIMER_Out_5; pwmParam.level = kSCTIMER_HighTrue; pwmParam.dutyCyclePercent = 5; SCTIMER_SetupPwm(SCT0, &pwmParam, kSCTIMER_CenterAlignedPwm, 1000U, CLOCK_GetFreq(kCLOCK_Sct), &event); } lcd_framebuffer = rt_malloc_align(sizeof(rt_uint16_t) * RT_HW_LCD_HEIGHT * RT_HW_LCD_WIDTH, 32); rt_memset(lcd_framebuffer, 0, sizeof(rt_uint16_t) * RT_HW_LCD_HEIGHT * RT_HW_LCD_WIDTH); { /* Initialize the display. */ lcdc_config_t lcdConfig; LCDC_GetDefaultConfig(&lcdConfig); lcdConfig.panelClock_Hz = LCD_PANEL_CLK; lcdConfig.ppl = LCD_PPL; lcdConfig.hsw = LCD_HSW; lcdConfig.hfp = LCD_HFP; lcdConfig.hbp = LCD_HBP; lcdConfig.lpp = LCD_LPP; lcdConfig.vsw = LCD_VSW; lcdConfig.vfp = LCD_VFP; lcdConfig.vbp = LCD_VBP; lcdConfig.polarityFlags = LCD_POL_FLAGS; lcdConfig.upperPanelAddr = (uint32_t)lcd_framebuffer;//VRAM_ADDR; lcdConfig.bpp = kLCDC_16BPP565; lcdConfig.display = kLCDC_DisplayTFT; lcdConfig.swapRedBlue = true; LCDC_Init(LCD, &lcdConfig, CLOCK_GetFreq(kCLOCK_LCD)); /* Trigger interrupt at start of every vertical back porch. */ LCDC_SetVerticalInterruptMode(LCD, kLCDC_StartOfBackPorch); LCDC_EnableInterrupts(LCD, kLCDC_VerticalCompareInterrupt); NVIC_EnableIRQ(LCD_IRQn); LCDC_Start(LCD); LCDC_PowerUp(LCD); } return RT_EOK; }