void nl_resize_socket_buffer(struct nfct_handle *h)
{
unsigned int s = CONFIG(netlink_buffer_size);
/* already warned that we have reached the maximum buffer size */
if (warned)
return;
/* since sock_setsockopt in net/core/sock.c doubles the size of socket
buffer passed to it using nfnl_rcvbufsiz, only call nfnl_rcvbufsiz
if new value is not greater than netlink_buffer_size_max_grown */
if (s*2 > CONFIG(netlink_buffer_size_max_grown)) {
dlog(LOG_WARNING,
"netlink event socket buffer size cannot "
"be doubled further since it will exceed "
"NetlinkBufferSizeMaxGrowth. We are likely to "
"be losing events, this may lead to "
"unsynchronized replicas. Please, consider "
"increasing netlink socket buffer size via "
"NetlinkBufferSize and "
"NetlinkBufferSizeMaxGrowth clauses in "
"conntrackd.conf");
warned = 1;
return;
}
CONFIG(netlink_buffer_size) = nfnl_rcvbufsiz(nfct_nfnlh(h), s);
/* notify the sysadmin */
dlog(LOG_NOTICE, "netlink event socket buffer size has been doubled "
"to %u bytes", CONFIG(netlink_buffer_size));
}
static void bochs_init(struct device *dev)
{
if (CONFIG(LINEAR_FRAMEBUFFER))
bochs_init_linear_fb(dev);
else if (CONFIG(VGA_TEXT_FRAMEBUFFER))
bochs_init_text_mode(dev);
}
void acpi_create_gnvs(struct global_nvs_t *gnvs)
{
const struct device *dev = PCH_DEV_LPC;
const struct soc_intel_icelake_config *config = dev->chip_info;
/* Set unknown wake source */
gnvs->pm1i = -1;
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
if (CONFIG(CONSOLE_CBMEM))
/* Update the mem console pointer. */
gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
if (CONFIG(CHROMEOS)) {
/* Initialize Verified Boot data */
chromeos_init_chromeos_acpi(&(gnvs->chromeos));
if (CONFIG(EC_GOOGLE_CHROMEEC)) {
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
} else
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
}
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = config->dptf_enable;
/* Fill in the Wifi Region id */
gnvs->cid1 = wifi_regulatory_domain();
/* Set USB2/USB3 wake enable bitmaps. */
gnvs->u2we = config->usb2_wake_enable_bitmap;
gnvs->u3we = config->usb3_wake_enable_bitmap;
}
void board_BeforeAgesa(struct sysinfo *cb)
{
u8 byte;
/* Enable the AcpiMmio space */
outb(0x24, 0xcd6);
outb(0x1, 0xcd7);
/* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);
if (CONFIG(POST_DEVICE_PCI_PCIE))
hudson_pci_port80();
if (CONFIG(POST_DEVICE_LPC))
hudson_lpc_port80();
/* enable SIO LPC decode */
byte = pci_read_config8(dev, 0x48);
byte |= 3; /* 2e, 2f */
pci_write_config8(dev, 0x48, byte);
/* enable serial decode */
byte = pci_read_config8(dev, 0x44);
byte |= (1 << 6); /* 0x3f8 */
pci_write_config8(dev, 0x44, byte);
/* run ite */
sbxxx_enable_48mhzout();
ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);
ite_kill_watchdog(GPIO_DEV);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}
floatms_t WallFuel::adjust(int injectorIndex, floatms_t target DECLARE_ENGINE_PARAMETER_SUFFIX) {
if (cisnan(target)) {
return target;
}
// disable this correction for cranking
if (ENGINE(rpmCalculator).isCranking(PASS_ENGINE_PARAMETER_SIGNATURE)) {
return target;
}
float addedToWallCoef = CONFIG(addedToWallCoef);
/**
* What amount of fuel is sucked of the walls, based on current amount of fuel on the wall.
*/
floatms_t suckedOffWallsAmount = wallFuel[injectorIndex] * CONFIG(suckedOffCoef);
floatms_t adjustedFuelPulse = (target - suckedOffWallsAmount) / (1 - addedToWallCoef);
// We can't inject a negative amount of fuel
// If this goes below zero we will be over-fueling slightly,
// but that's ok.
if(adjustedFuelPulse < 0) {
adjustedFuelPulse = 0;
}
float addedToWallsAmount = adjustedFuelPulse * addedToWallCoef;
wallFuel[injectorIndex] += addedToWallsAmount - suckedOffWallsAmount;
engine->wallFuelCorrection = adjustedFuelPulse - target;
return adjustedFuelPulse;
}
void nl_resize_socket_buffer(struct nfct_handle *h)
{
unsigned int s = CONFIG(netlink_buffer_size) * 2;
/* already warned that we have reached the maximum buffer size */
if (warned)
return;
if (s > CONFIG(netlink_buffer_size_max_grown)) {
dlog(STATE(log), "WARNING: maximum netlink socket buffer "
"size has been reached. We are likely to "
"be losing events, this may lead to "
"unsynchronized replicas. Please, consider "
"increasing netlink socket buffer size via "
"SocketBufferSize and "
"SocketBufferSizeMaxGrown clauses in "
"conntrackd.conf");
s = CONFIG(netlink_buffer_size_max_grown);
warned = 1;
}
CONFIG(netlink_buffer_size) = nfnl_rcvbufsiz(nfct_nfnlh(h), s);
/* notify the sysadmin */
dlog(STATE(log), "netlink socket buffer size has been set to %u bytes",
CONFIG(netlink_buffer_size));
}
/**
* This function adds an error if MAP sensor value is outside of expected range
* @return unchanged mapKPa parameter
*/
float validateMap(float mapKPa DECLARE_ENGINE_PARAMETER_S) {
if (cisnan(mapKPa) || mapKPa < CONFIG(mapErrorLowValue) || mapKPa > CONFIG(mapErrorHighValue)) {
warning(OBD_PCM_Processor_Fault, "invalid MAP value: %f", mapKPa);
return 0;
}
return mapKPa;
}
static void save_memory_training_data(bool s3wake, uint32_t fsp_version)
{
size_t mrc_data_size;
const void *mrc_data;
if (!CONFIG(CACHE_MRC_SETTINGS) || s3wake)
return;
mrc_data = fsp_find_nv_storage_data(&mrc_data_size);
if (!mrc_data) {
printk(BIOS_ERR, "Couldn't find memory training data HOB.\n");
return;
}
/*
* Save MRC Data to CBMEM. By always saving the data this forces
* a retrain after a trip through Chrome OS recovery path. The
* code which saves the data to flash doesn't write if the latest
* training data matches this one.
*/
if (mrc_cache_stash_data(MRC_TRAINING_DATA, fsp_version, mrc_data,
mrc_data_size) < 0)
printk(BIOS_ERR, "Failed to stash MRC data\n");
if (CONFIG(FSP2_0_USES_TPM_MRC_HASH))
mrc_cache_update_hash(mrc_data, mrc_data_size);
}
static void fill_console_params(FSPM_UPD *mupd)
{
if (CONFIG(CONSOLE_SERIAL)) {
if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) {
mupd->FspmConfig.SerialDebugPortDevice =
CONFIG_UART_FOR_CONSOLE;
/* use MMIO port type */
mupd->FspmConfig.SerialDebugPortType = 2;
/* use 4 byte register stride */
mupd->FspmConfig.SerialDebugPortStrideSize = 2;
/* used only for port type set to external */
mupd->FspmConfig.SerialDebugPortAddress = 0;
} else if (CONFIG(DRIVERS_UART_8250IO)) {
/* use external UART for debug */
mupd->FspmConfig.SerialDebugPortDevice = 3;
/* use I/O port type */
mupd->FspmConfig.SerialDebugPortType = 1;
/* use 1 byte register stride */
mupd->FspmConfig.SerialDebugPortStrideSize = 0;
/* used only for port type set to external */
mupd->FspmConfig.SerialDebugPortAddress =
CONFIG_TTYS0_BASE;
}
} else {
mupd->FspmConfig.SerialDebugPortType = 0;
}
}
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchReset->Xhci1Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchReset->SataEnable = 1;
FchReset->IdeEnable = 0;
}
bool TrackingBruteForce::initialize(configuration::ConfigurationManager& settings) {
isInitialized = true;
CONFIG(settings, maximumDistance, "TrackingMaximumDistance", 4000);
CONFIG(settings, minimumLifeSpan, "TrackingMinimumLifeSpan", 15); //Currently # Frames, should be in ms...
CONFIG(settings, maximumTimeLostInDoorArea, "MaximumTimeLostInDoorArea", 9); //Currently # Frames, should be in ms...
CONFIG(settings, maximumTimeLostStill, "MaximumTimeLostInDoorArea", 100);
return isInitialized;
}
/*
Request:
MUST NOT have extras.
MUST have key.
MUST have value.
*/
ST_RES *cmd_code_load(CONN *conn, ST_REQ *req, ST_RES *res) {
if(req->extras_sz || !req->key_sz || !req->value_sz)
return(set_error_code(res, MEMCACHE_STATUS_INVALID_ARGUMENTS, NULL));
if(CONFIG(conn)->vx32_disabled) {
return(set_error_code(res, MEMCACHE_STATUS_UNKNOWN_COMMAND, "Command disabled by configuration"));
}
if(NULL != find_process(req->key, req->key_sz))
return(set_error_code(res, MEMCACHE_STATUS_KEY_EXISTS, NULL));
int r;
char c_file[1024];
char elf_file[1024];
char keyprefix[32];
key_escape(keyprefix, sizeof(keyprefix), req->key, req->key_sz);
keyprefix[MIN(req->key_sz, sizeof(keyprefix)-1)] = '\0'; // make it reasonably short
snprintf(c_file, sizeof(c_file), "%s/plugin-%s.c", CONFIG(conn)->tmpdir, keyprefix);
snprintf(elf_file, sizeof(elf_file), "%s/plugin-%s.elf", CONFIG(conn)->tmpdir, keyprefix);
res->value = res->buf;
r = write_file(c_file, req->value, req->value_sz);
if(0 != r) { // never
res->status = MEMCACHE_STATUS_ITEM_NOT_STORED;
res->value_sz += snprintf(&res->value[res->value_sz], res->buf_sz - res->value_sz, "Error while saving file: %s", strerror(errno));
return(res);
}
if(0 != process_compile(CONFIG(conn), c_file, elf_file, res->value, res->buf_sz, (int*)&res->value_sz)) {
res->status = MEMCACHE_STATUS_ITEM_NOT_STORED;
return(res);
}
res->value_sz = MIN(res->value_sz, 4096); // no more than 4k logs
res->value[res->value_sz++] = '\n';
res->value[res->value_sz++] = '\n';
struct process *process = process_new(conn, req->key, req->key_sz);
log_warn("#%p: loaded code", process);
r = process_load(process, elf_file);
if(0 != r) { // never
process_free(process);
res->value_sz += snprintf(&res->value[res->value_sz], res->buf_sz - res->value_sz, "Error while loading the binary");
res->status = MEMCACHE_STATUS_ITEM_NOT_STORED;
return(res);
}
if(0 != process_run(conn, process)) {
process_free(process);
res->value_sz += snprintf(&res->value[res->value_sz], res->buf_sz - res->value_sz, "Error while running the binary");
res->status = MEMCACHE_STATUS_ITEM_NOT_STORED;
return(res);
}
res->status = MEMCACHE_STATUS_OK;
return res;
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
struct region_device rdev;
check_full_retrain(mupd);
fill_console_params(mupd);
if (CONFIG(SOC_INTEL_GLK))
soc_memory_init_params(mupd);
mainboard_memory_init_params(mupd);
parse_devicetree_setting(mupd);
/* Do NOT let FSP do any GPIO pad configuration */
mupd->FspmConfig.PreMemGpioTablePtr = (uintptr_t) NULL;
/*
* Tell CSE we do not need to use Ring Buffer Protocol (RBP) to fetch
* firmware for us if we are using memory-mapped SPI. This lets CSE
* state machine transition to next boot state, so that it can function
* as designed.
*/
mupd->FspmConfig.SkipCseRbp =
CONFIG(BOOT_DEVICE_MEMORY_MAPPED);
/*
* Converged Security Engine (CSE) has secure storage functionality.
* HECI2 device can be used to access that functionality. However, part
* of S3 resume flow involves resetting HECI2 which takes 136ms. Since
* coreboot does not use secure storage functionality, instruct FSP to
* skip HECI2 reset.
*/
mupd->FspmConfig.EnableS3Heci2 = 0;
/*
* Apollolake splits MRC cache into two parts: constant and variable.
* The constant part is not expected to change often and variable is.
* Currently variable part consists of parameters that change on cold
* boots such as scrambler seed and some memory controller registers.
* Scrambler seed is vital for S3 resume case because attempt to use
* wrong/missing key renders DRAM contents useless.
*/
if (mrc_cache_get_current(MRC_VARIABLE_DATA, version, &rdev) == 0) {
/* Assume leaking is ok. */
assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
mupd->FspmConfig.VariableNvsBufferPtr = rdev_mmap_full(&rdev);
}
car_set_var(fsp_version, version);
}
void car_soc_pre_console_init(void)
{
/* Initialize the controllers */
reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init);
reg_script_run_on_dev(LPC_BDF, legacy_gpio_init);
/* Enable the HSUART */
if (CONFIG(ENABLE_BUILTIN_HSUART0))
reg_script_run_on_dev(HSUART0_BDF, hsuart_init);
if (CONFIG(ENABLE_BUILTIN_HSUART1))
reg_script_run_on_dev(HSUART1_BDF, hsuart_init);
}
int main(int argc, char ** argv)
{
unsigned long size;
long hpage_size;
int pid, status;
int i;
int wait_list[MAX_PROCS];
test_init(argc, argv);
if (argc < 3)
CONFIG("Usage: %s <# procs> <# pages>", argv[0]);
numprocs = atoi(argv[1]);
nr_hugepages = atoi(argv[2]);
if (numprocs > MAX_PROCS)
CONFIG("Cannot spawn more than %d processes", MAX_PROCS);
check_hugetlb_shm_group();
hpage_size = check_hugepagesize();
size = hpage_size * nr_hugepages;
verbose_printf("Requesting %lu bytes\n", size);
if ((shmid = shmget(2, size, SHM_HUGETLB|IPC_CREAT|SHM_R|SHM_W )) < 0)
FAIL("shmget(): %s", strerror(errno));
verbose_printf("shmid: %d\n", shmid);
verbose_printf("Spawning children:\n");
for (i=0; i<numprocs; i++) {
if ((pid = fork()) < 0)
FAIL("fork(): %s", strerror(errno));
if (pid == 0)
do_child(i, size);
wait_list[i] = pid;
}
for (i=0; i<numprocs; i++) {
waitpid(wait_list[i], &status, 0);
if (WEXITSTATUS(status) != 0)
FAIL("Thread %d (pid=%d) failed", i, wait_list[i]);
if (WIFSIGNALED(status))
FAIL("Thread %d (pid=%d) received unhandled signal",
i, wait_list[i]);
}
PASS();
}
int display_init_required(void)
{
/* For vboot always honor vboot_handoff_skip_display_init(). */
if (CONFIG(VBOOT)) {
/* Must always select OPROM_MATTERS when using this function. */
if (!CONFIG(VBOOT_OPROM_MATTERS))
dead_code();
return !vboot_handoff_skip_display_init();
}
/* By default always initialize display. */
return 1;
}
/*
* Enable TCO BAR using SMBUS TCO base to access TCO related register
* also disable the timer.
*/
void tco_configure(void)
{
if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS))
tco_enable_bar();
tco_timer_disable();
}
static timestamp_t
init(void * self, char *args[])
{
config_t * config;
int i;
pkt_t *pkt;
metadesc_t *inmd;
config = mem_mdl_malloc(self, sizeof(config_t));
config->meas_ivl = 1;
config->iface = -1;
for (i = 0; args && args[i]; i++) {
char * wh;
wh = index(args[i], '=') + 1;
if (strstr(args[i], "interval")) {
config->meas_ivl = atoi(wh);
} else if (strstr(args[i], "interface")) {
config->iface = atoi(wh);
}
}
/* setup indesc */
inmd = metadesc_define_in(self, 0);
inmd->ts_resolution = TIME2TS(config->meas_ivl, 0);
pkt = metadesc_tpl_add(inmd, "none:none:none:none");
CONFIG(self) = config;
return TIME2TS(config->meas_ivl, 0);
}
static int
update(void * self, pkt_t *pkt, void *fh, int isnew)
{
FLOWDESC *x = F(fh);
config_t * cf = CONFIG(self);
if (isnew) {
bzero(x, sizeof(FLOWDESC));
x->ts = COMO(ts);
}
if (COMO(type) == COMOTYPE_NF) {
if (cf->iface == -1 || H16(NF(input)) == cf->iface) {
x->bytes[0] += H32(NF(pktcount)) * COMO(len) * H16(NF(sampling));
x->pkts[0] += H32(NF(pktcount)) * (uint32_t) H16(NF(sampling));
} else if (H16(NF(output)) == cf->iface) {
x->bytes[1] += H32(NF(pktcount)) * COMO(len) * H16(NF(sampling));
x->pkts[1] += H32(NF(pktcount)) * (uint32_t) H16(NF(sampling));
}
} else if (COMO(type) == COMOTYPE_SFLOW) {
x->bytes[0] += (uint64_t) COMO(len) *
(uint64_t) H32(SFLOW(sampling_rate));
x->pkts[0] += H32(SFLOW(sampling_rate));
} else {
x->bytes[0] += COMO(len);
x->pkts[0]++;
}
return 0;
}
void check_free_huge_pages(int nr_pages_needed)
{
long hpage_size = gethugepagesize();
int freepages = get_huge_page_counter(hpage_size, HUGEPAGES_FREE);
if (freepages < nr_pages_needed)
CONFIG("Must have at least %i free hugepages", nr_pages_needed);
}
int mainboard_smi_apmc(u8 apmc)
{
if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
MAINBOARD_EC_SMI_EVENTS);
return 0;
}
MODULE check_if_automatic_signon (THREAD *thread)
{
if (*CONFIG ("ddns:enabled") == '1')
the_next_event = ok_event;
else
the_next_event = ignore_event;
}
int main(int argc, char *argv[])
{
void *sohandle;
void *fdt;
int err;
test_init(argc, argv);
if (argc != 2)
CONFIG("Usage: %s <so file>", argv[0]);
sohandle = dlopen(argv[1], RTLD_NOW);
if (!sohandle)
FAIL("Couldn't dlopen() %s", argv[1]);
fdt = dlsym(sohandle, "dt_blob_start");
if (!fdt)
FAIL("Couldn't locate \"dt_blob_start\" symbol in %s",
argv[1]);
err = fdt_check_header(fdt);
if (err != 0)
FAIL("%s contains invalid tree: %s", argv[1],
fdt_strerror(err));
check_prop_labels(sohandle, fdt, "prop1", labels1, ARRAY_SIZE(labels1));
check_prop_labels(sohandle, fdt, "prop2", labels2, ARRAY_SIZE(labels2));
check_prop_labels(sohandle, fdt, "prop3", labels3, ARRAY_SIZE(labels3));
PASS();
}
static void disable_unused_touchscreen(void *unused)
{
struct device *i2c0 = PCH_DEV_I2C0;
struct bus *i2c_slaves = i2c0->link_list;
struct device *slave = i2c_slaves->children;
char touchscreen_hid[9] = CONFIG_TOUCHSCREEN_HID;
struct drivers_i2c_hid_config *info;
/* Look for VPD key that indicates which touchscreen is present */
if (CONFIG(VPD) &&
!vpd_gets(TOUCHSCREEN_VPD_KEY, touchscreen_hid,
ARRAY_SIZE(touchscreen_hid), VPD_ANY))
printk(BIOS_INFO, "%s: VPD key '%s' not found, default to %s\n",
__func__, TOUCHSCREEN_VPD_KEY, touchscreen_hid);
/* Go through all I2C slave devices on this bus */
while (slave) {
/* Find all the I2C slaves with the matching address */
if (slave->path.type == DEVICE_PATH_I2C &&
slave->path.i2c.device == TOUCHSCREEN_I2C_ADDR) {
info = slave->chip_info;
/* Disable all devices except the matching HID */
if (strncmp(info->generic.hid, touchscreen_hid,
ARRAY_SIZE(touchscreen_hid))) {
printk(BIOS_INFO, "%s: Disable %s\n", __func__,
info->generic.hid);
slave->enabled = 0;
} else {
printk(BIOS_INFO, "%s: Enable %s\n", __func__,
info->generic.hid);
}
}
slave = slave->sibling;
}
}
/* Locate VBT and pass it to FSP GOP */
void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params)
{
const optionrom_vbt_t *vbt_data = NULL;
size_t vbt_len;
/* Check boot mode - for S3 resume path VBT loading is not needed */
if (s3_resume) {
printk(BIOS_DEBUG, "S3 resume do not pass VBT to GOP\n");
} else if (display_init_required()) {
/* Get VBT data */
vbt_data = locate_vbt(&vbt_len);
if (vbt_data != NULL) {
if (CONFIG(DISPLAY_VBT)) {
/* Display the vbt file contents */
printk(BIOS_DEBUG, "VBT Data:\n");
hexdump(vbt_data, vbt_len);
printk(BIOS_DEBUG, "\n");
}
printk(BIOS_DEBUG, "Passing VBT to GOP\n");
} else {
printk(BIOS_DEBUG, "VBT not found!\n");
}
} else {
printk(BIOS_DEBUG, "Not passing VBT to GOP\n");
}
params->GraphicsConfigPtr = (u32)vbt_data;
}
static void acpi_jump_to_wakeup(void *vector)
{
uintptr_t source = 0, target = 0;
size_t size = 0;
if (!acpi_s3_resume_allowed()) {
printk(BIOS_WARNING, "ACPI: S3 resume not allowed.\n");
return;
}
if (!CONFIG(RELOCATABLE_RAMSTAGE)) {
struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME);
if (backup_mem && backup_mem->valid) {
backup_mem->valid = 0;
target = backup_mem->lowmem;
source = backup_mem->cbmem;
size = backup_mem->size;
} else {
printk(BIOS_WARNING, "ACPI: Backup memory missing. "
"No S3 resume.\n");
return;
}
}
/* Copy wakeup trampoline in place. */
memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size);
set_boot_successful();
timestamp_add_now(TS_ACPI_WAKE_JUMP);
acpi_do_wakeup((uintptr_t)vector, source, target, size);
}
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
if (CONFIG(ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY))
light_sd_led();
bootblock_main_with_timestamp(base_timestamp, NULL, 0);
}
static timestamp_t
init(void * self, char *args[])
{
CONFIGDESC * config;
int i;
pkt_t *pkt;
metadesc_t *inmd;
config = mem_mdl_malloc(self, sizeof(CONFIGDESC));
config->meas_ivl = 1;
for (i = 0; args && args[i]; i++) {
if (strstr(args[i], "interval")) {
char * val = index(args[i], '=') + 1;
config->meas_ivl = atoi(val);
}
}
/* setup indesc */
inmd = metadesc_define_in(self, 0);
inmd->ts_resolution = TIME2TS(config->meas_ivl, 0);
pkt = metadesc_tpl_add(inmd, "none:none:none:none");
/* inmd = metadesc_define_in(self, 1, "sampling_rate");
pkt = metadesc_tpl_add(inmd, "none:none:none:none");*/
CONFIG(self) = config;
return TIME2TS(config->meas_ivl, 0);
}
static int one_racer(void *p, int cpu,
volatile int *mytrigger, volatile int *othertrigger)
{
volatile int *pi = p;
cpu_set_t cpuset;
int err;
/* Split onto different cpus to encourage the race */
CPU_ZERO(&cpuset);
CPU_SET(cpu, &cpuset);
err = sched_setaffinity(gettid(), CPU_SETSIZE/8, &cpuset);
if (err != 0)
CONFIG("sched_setaffinity(cpu%d): %s", cpu, strerror(errno));
/* Ready.. */
*mytrigger = 1;
/* Set.. */
while (! *othertrigger)
;
/* Instantiate! */
*pi = 1;
return 0;
}
void bootblock_soc_init(void)
{
if (CONFIG(ENABLE_DEBUG_LED_SOC_INIT_ENTRY))
light_sd_led();
display_mtrrs();
}
