static int
ks8695p_write_config_word(struct pci_dev *dev, int where, u16 value)
{
u32 reg, shift;
#ifdef DEBUG_THIS
printk(KERN_INFO "%s\n", __FUNCTION__);
#endif
shift = where & 0x00000002;
KS8695_WRITE(KS8695_2100, CONFIG_CMD(dev, where));
reg = KS8695_READ(KS8695_2104);
switch (shift) {
case 2:
reg &= 0x0000ffff;
reg |= (u32)value << 16;
break;
default:
reg &= 0xffff0000;
reg |= (u32)value;
break;
}
KS8695_WRITE(KS8695_2100, CONFIG_CMD(dev, where));
KS8695_WRITE(KS8695_2104, reg);
return PCIBIOS_SUCCESSFUL;
}
static int
via82c505_write_config_dword(struct pci_dev *dev, int where, u32 value)
{
outl(CONFIG_CMD(dev,where),0xCF8);
outl(value, 0xCFC);
return PCIBIOS_SUCCESSFUL;
}
static int
via82c505_write_config_byte(struct pci_dev *dev, int where, u8 value)
{
outl(CONFIG_CMD(dev,where),0xCF8);
outb(value, 0xCFC + (where&3));
return PCIBIOS_SUCCESSFUL;
}
static int
via82c505_read_config_dword(struct pci_dev *dev, int where, u32 *value)
{
outl(CONFIG_CMD(dev,where),0xCF8);
*value=inl(0xCFC);
return PCIBIOS_SUCCESSFUL;
}
static int
via82c505_read_config_byte(struct pci_dev *dev, int where, u8 *value)
{
outl(CONFIG_CMD(dev,where),0xCF8);
*value=inb(0xCFC + (where&3));
return PCIBIOS_SUCCESSFUL;
}
VOID
XboxMemInit(VOID)
{
UCHAR ControlRegion[TEST_SIZE];
PVOID MembaseTop = (PVOID)(64 * 1024 * 1024);
PVOID MembaseLow = (PVOID)0;
(*(PULONG)(0xfd000000 + 0x100200)) = 0x03070103 ;
(*(PULONG)(0xfd000000 + 0x100204)) = 0x11448000 ;
WRITE_PORT_ULONG((ULONG*) 0xcf8, CONFIG_CMD(0, 0, 0x84));
WRITE_PORT_ULONG((ULONG*) 0xcfc, 0x7ffffff); /* Prep hardware for 128 Mb */
InstalledMemoryMb = 64;
memset(ControlRegion, TEST_PATTERN1, TEST_SIZE);
memset(MembaseTop, TEST_PATTERN1, TEST_SIZE);
__wbinvd();
if (0 == memcmp(MembaseTop, ControlRegion, TEST_SIZE))
{
/* Looks like there is memory .. maybe a 128MB box */
memset(ControlRegion, TEST_PATTERN2, TEST_SIZE);
memset(MembaseTop, TEST_PATTERN2, TEST_SIZE);
__wbinvd();
if (0 == memcmp(MembaseTop, ControlRegion, TEST_SIZE))
{
/* Definitely looks like there is memory */
if (0 == memcmp(MembaseLow, ControlRegion, TEST_SIZE))
{
/* Hell, we find the Test-string at 0x0 too ! */
InstalledMemoryMb = 64;
}
else
{
InstalledMemoryMb = 128;
}
}
}
/* Set hardware for amount of memory detected */
WRITE_PORT_ULONG((ULONG*) 0xcf8, CONFIG_CMD(0, 0, 0x84));
WRITE_PORT_ULONG((ULONG*) 0xcfc, InstalledMemoryMb * 1024 * 1024 - 1);
AvailableMemoryMb = InstalledMemoryMb;
}
static int
ks8695p_write_config_dword(struct pci_dev *dev, int where, u32 value)
{
#ifdef DEBUG_THIS
printk(KERN_INFO "%s\n", __FUNCTION__);
#endif
KS8695_WRITE(KS8695_2100, CONFIG_CMD(dev, where));
KS8695_WRITE(KS8695_2104, value);
return PCIBIOS_SUCCESSFUL;
}
static int
ks8695p_read_config_dword(struct pci_dev *dev, int where, u32 *value)
{
#ifdef DEBUG_THIS
printk(KERN_INFO "%s\n", __FUNCTION__);
#endif
KS8695_WRITE(KS8695_2100, CONFIG_CMD(dev, where));
*value = KS8695_READ(KS8695_2104);
#ifdef DEBUG_THIS
printk(KERN_INFO "%s: value=0x%08x\n", __FUNCTION__, *value);
#endif
return PCIBIOS_SUCCESSFUL;
}
static int pci_ampci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
int where, u32 value)
{
u32 rawval;
if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
__pcbdebug("<= %08x", &BRIDGEREGL(where), value);
BRIDGEREGL(where) = value;
} else {
if (__query(bus, devfn))
__pcidebug("<= %08x", bus, devfn, where, value);
CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where);
rawval = CONFIG_ADDRESS;
CONFIG_DATAL(where) = value;
}
return PCIBIOS_SUCCESSFUL;
}
static int
via82c505_read_config(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 *value)
{
outl(CONFIG_CMD(bus,devfn,where),0xCF8);
switch (size) {
case 1:
*value=inb(0xCFC + (where&3));
break;
case 2:
*value=inw(0xCFC + (where&2));
break;
case 4:
*value=inl(0xCFC);
break;
}
return PCIBIOS_SUCCESSFUL;
}
static int
via82c505_write_config(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 value)
{
outl(CONFIG_CMD(bus,devfn,where),0xCF8);
switch (size) {
case 1:
outb(value, 0xCFC + (where&3));
break;
case 2:
outw(value, 0xCFC + (where&2));
break;
case 4:
outl(value, 0xCFC);
break;
}
return PCIBIOS_SUCCESSFUL;
}
static int sh5pci_read(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 *val)
{
SH5PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
switch (size) {
case 1:
*val = (u8)SH5PCI_READ_BYTE(PDR + (where & 3));
break;
case 2:
*val = (u16)SH5PCI_READ_SHORT(PDR + (where & 2));
break;
case 4:
*val = SH5PCI_READ(PDR);
break;
}
return PCIBIOS_SUCCESSFUL;
}
static int pci_ampci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
int where, u32 *_value)
{
u32 rawval, value;
if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
value = BRIDGEREGL(where);
__pcbdebug("=> %08x", &BRIDGEREGL(where), value);
} else {
CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where);
rawval = CONFIG_ADDRESS;
value = CONFIG_DATAL(where);
if (__query(bus, devfn))
__pcidebug("=> %08x", bus, devfn, where, value);
}
*_value = value;
return PCIBIOS_SUCCESSFUL;
}
static int sh5pci_write(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 val)
{
SH5PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
switch (size) {
case 1:
SH5PCI_WRITE_BYTE(PDR + (where & 3), (u8)val);
break;
case 2:
SH5PCI_WRITE_SHORT(PDR + (where & 2), (u16)val);
break;
case 4:
SH5PCI_WRITE(PDR, val);
break;
}
return PCIBIOS_SUCCESSFUL;
}
static int pci_ampci_write_config_byte(struct pci_bus *bus, unsigned int devfn,
int where, u8 value)
{
u32 rawval;
if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
__pcbdebug("<= %02x", &BRIDGEREGB(where), value);
BRIDGEREGB(where) = value;
} else {
if (bus->number == 0 &&
(devfn == PCI_DEVFN(2, 0) || devfn == PCI_DEVFN(3, 0))
)
__pcidebug("<= %02x", bus, devfn, where, value);
CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where);
rawval = CONFIG_ADDRESS;
CONFIG_DATAB(where) = value;
}
return PCIBIOS_SUCCESSFUL;
}
static int
ks8695p_read_config_word(struct pci_dev *dev, int where, u16 *value)
{
u32 reg, shift;
#ifdef DEBUG_THIS
printk(KERN_INFO "%s\n", __FUNCTION__);
#endif
shift = where & 0x00000002;
KS8695_WRITE(KS8695_2100, CONFIG_CMD(dev, where));
reg = KS8695_READ(KS8695_2104);
*value = (u16)(reg >> (shift * 8));
#ifdef DEBUG_THIS
printk(KERN_INFO "%s: value=0x%04x\n", __FUNCTION__, *value);
#endif
return PCIBIOS_SUCCESSFUL;
}
static int
ks8695p_read_config_byte(struct pci_dev *dev, int where, u8 *value)
{
u32 reg, shift;
#ifdef DEBUG_THIS
printk(KERN_INFO "%s: bus=%d\n", __FUNCTION__, dev->bus->number);
#endif
/*RLQ, actually there is not need to do shift since the caller will guarantee alignment */
shift = where & 0x00000003;
KS8695_WRITE(KS8695_2100, CONFIG_CMD(dev, where));
reg = KS8695_READ(KS8695_2104);
*value = (u8)(reg >> (shift * 8));
#ifdef DEBUG_THIS
printk(KERN_INFO "%s: value=0x%02x\n", __FUNCTION__, *value);
#endif
return PCIBIOS_SUCCESSFUL;
}
static uint8_t pci_conf1_read_config8(struct bus *pbus, int bus, int devfn, int where)
{
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
return inb(0xCFC + (where & 3));
}
static uint32_t pci_conf1_read_config32(struct bus *pbus, int bus, int devfn, int where)
{
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
return inl(0xCFC);
}
static void pci_conf1_write_config16(struct bus *pbus, int bus, int devfn, int where, uint16_t value)
{
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
outw(value, 0xCFC + (where & 2));
}
static int
wmt_read_config(
struct pci_bus *bus,
unsigned int devfn,
int where,
int size,
u32 *value
)
{
u32 bar, mask, devno, func;
devno = devfn >> 3;
func = devfn & 7;
*value = 0xFFFFFFFF;
#ifndef EXT_PCI
if (devno > 6)
return 0;
#endif
switch (devno) { /* Check the dev number */
/* external PCI devices */
case EXT_PCI7:
case EXT_PCI8:
case EXT_PCI9:
case EXT_PCIA:
case EXT_PCIB:
{
if ((where >= 0x10) && (where < 0x28)) {
switch (size) {
case 1:
bar = (where & ~3)/4;
mask = 0xFF << 8*(where & 3);
*value = pci_config_shadow[devno][func][bar] & mask;
*value = (*value) >> 8*(where & 3);
break;
case 2:
bar = (where & ~3)/4;
mask = 0xFFFF << 8*(where & 2);
*value = pci_config_shadow[devno][func][bar] & mask;
*value = (*value) >> 8*(where & 2);
break;
case 4:
bar = (where & ~3)/4;
mask = 0xFFFFFFFF;
*value = pci_config_shadow[devno][func][bar] & mask;
}
} else {
writel(CONFIG_CMD(bus, devfn, where), pci_config_addr);
switch (size) {
case 1:
*value = readb(pci_config_data + (where&3));
break;
case 2:
*value = readw(pci_config_data + (where&2));
break;
case 4:
*value = readl(pci_config_data);
break;
}
}
}
break;
/* internal PCI devices */
#ifdef SATA
case INT_SATA:
if ((where >= 0xA0) && (where <= 0xAF)) {
switch (size) {
case 1:
*value = inb((SATA_PCI_CONFIG + where));
break;
case 2:
*value = inw((SATA_PCI_CONFIG + (where & ~1)));
break;
case 4:
*value = inl((SATA_PCI_CONFIG + (where & ~3)));
break;
}
break;
}
#endif
case INT_PATA:
case INT_MAC0:
case INT_MAC1:
if (devfn & 7)
break;
switch (size) {
case 1:
if ((where < 0x40)) {
bar = (where & ~3)/4;
mask = 0xFF << 8*(where & 3);
*value = pci_config_shadow[devno][0][bar] & mask;
*value = (*value) >> 8*(where & 3);
} else
static void pci_conf1_write_config32(struct bus *pbus, int bus, int devfn, int where, uint32_t value)
{
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
outl(value, 0xCFC);
}
static uint16_t pci_conf1_read_config16(struct bus *pbus, int bus, int devfn, int where)
{
outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
return inw(0xCFC + (where & 2));
}
