void start_settings(void)
{
// Init MMU
CP15_Mmu(FALSE); // Disable MMU
// Privileged permissions User permissions AP
// Read-only Read-only 0
CP15_SysProt(FALSE);
CP15_RomProt(TRUE);
CP15_InitMmuTtb(TtSB,TtTB); // Build L1 and L2 Translation tables
CP15_SetTtb(L1Table); // Set base address of the L1 Translation table
CP15_SetDomain( (DomainManager << 2*1) | (DomainClient << 0)); // Set domains
CP15_Mmu(TRUE); // Enable MMU
CP15_Cache(TRUE); // Enable ICache,DCache
/* Disable interrupts in ARM core */
disable_irq_fiq();
InitializeInterruptSystem();
// Enable IRQ interrupts in the ARM core
enable_irq_fiq();
initCallBackElement();//инит callBackElement
initTimers();//инит таймеров
initTimers_WL();//TIMERS INIT РЛ
WideLogActual = &(pActualCMD[DQUADRO]);//командный массив расшир логики(вторая половина)
ResetSystemMenu();//сбросить сист меню
timing = 0;
}//start_settings(void)
/* Called from cstartup.s before the kernel is started. */
void LowLevelInitialisation(void)
{
/* Chip configuration functions from IAR. ********************************/
/* Disable MMU, enable ICache */
CP15_Mmu(FALSE);
CP15_ICache(FALSE);
CP15_SetVectorBase( (uint32_t )__section_begin( ".intvec" ) );
/* Set Low vectors mode in CP15 Control Register */
CP15_SetHighVectors(FALSE);
/* Chip and board specific configuration functions from Renesas. *********/
Peripheral_BasicInit();
STB_Init();
PORT_Init();
R_BSC_Init( ( uint8_t ) ( BSC_AREA_CS2 | BSC_AREA_CS3 ) );
R_INTC_Init();
CP15_ICache(TRUE);
/* Start with interrupts enabled. */
__enable_irq();
__enable_fiq();
}
