OS_PRIO  OS_PrioGetHighest (void)
{
    CPU_DATA  *p_tbl;
    OS_PRIO    prio;


    prio  = (OS_PRIO)0;
    p_tbl = &OSPrioTbl[0];
    while (*p_tbl == (CPU_DATA)0) {                         /* Search the bitmap table for the highest priority       */
        prio += DEF_INT_CPU_NBR_BITS;                       /* Compute the step of each CPU_DATA entry                */
        p_tbl++;
    }
    prio += (OS_PRIO)CPU_CntLeadZeros(*p_tbl);              /* Find the position of the first bit set at the entry    */
    return (prio);
}
Esempio n. 2
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static  void  CSP_DMA_IntHandler (void *p_arg)
{    
    CSP_DMA_REG           *p_dma_reg;
    CSP_DMA_CH_REG        *p_dma_ch_reg; 
    CSP_DMA_CH            *p_dma_ch;
    void                  *p_callback_arg;
    CSP_DMA_CALLBACK_PTR   callback_fnct;
    CSP_DEV_NBR            ch_nbr;
    CPU_INT32U             int_tc_stat;
    CPU_INT32U             int_err_stat;
    CPU_BOOLEAN            status;
    CPU_INT16U             xfer_size_rem;

    
    p_dma_reg    = (CSP_DMA_REG *)CSP_ADDR_DMA_REG;    
    int_tc_stat  = p_dma_reg->IntTCStat  & DEF_BIT_FIELD(8u, 0u);
    int_err_stat = p_dma_reg->IntErrStat & DEF_BIT_FIELD(8u, 0u);
    
                                                                /* --------- INTERRUPT TERMINAL COUNT HANDLING -------- */
    while (int_tc_stat != DEF_BIT_NONE) {                       
                                                                /* Get current DMA channel number                       */
        ch_nbr               = 31u - CPU_CntLeadZeros(int_tc_stat);
        p_dma_ch_reg         = &(p_dma_reg->CHx[ch_nbr]);
        p_dma_ch             = &(CSP_DMA_ChTbl[ch_nbr]);

        callback_fnct        = p_dma_ch->CallBackFnctPtr;       /* Get the callback function                            */
        p_callback_arg       = p_dma_ch->CallBackArgPtr;        /* Get the callback argument pointer.                   */        
                                                                /* Get the remaining transfer size.                     */
        xfer_size_rem        = p_dma_ch_reg->Ctrl & DEF_BIT_FIELD(12u, 0u);
        p_dma_reg->IntTCClr  = DEF_BIT(ch_nbr);                 /* Clear the terminal count interrupt.                  */
        
        if (DEF_BIT_IS_SET(int_err_stat, DEF_BIT(ch_nbr))) {    /* If an error occured in the channel...                */
            status                = DEF_FAIL;                   /* ... set the status, and clear the error interrupt.   */
            p_dma_reg->IntErrClr = DEF_BIT(ch_nbr);
        } else {
            status                = DEF_OK;                     
        }
            
        callback_fnct(ch_nbr,                                   /* Call the callback function.                           */
                      xfer_size_rem,
                      p_callback_arg,
                      status);
                                                                /* Read the terminal count and error interrupts status   */
        int_tc_stat  = p_dma_reg->IntTCStat  & DEF_BIT_FIELD(8u, 0u);
        int_err_stat = p_dma_reg->IntErrStat & DEF_BIT_FIELD(8u, 0u);                            
    }
                                                                /* --------------- ERROR INTERRUPT HANDLING ------------ */
    int_err_stat = p_dma_reg->IntErrStat & DEF_BIT_FIELD(8u, 0u);
    
    while (int_err_stat != DEF_BIT_NONE) {
        ch_nbr               = 31u - CPU_CntLeadZeros(int_err_stat);
        p_dma_ch_reg         = &(p_dma_reg->CHx[ch_nbr]);
        p_dma_ch             = &(CSP_DMA_ChTbl[ch_nbr]);
        callback_fnct        = p_dma_ch->CallBackFnctPtr;
        p_callback_arg       = p_dma_ch->CallBackArgPtr;
        p_dma_ch->State      = CSP_DMA_CH_STATE_ALLOC;          /* Set the channel state = 'ALLOC'                      */
        xfer_size_rem        = p_dma_ch_reg->Ctrl & DEF_BIT_FIELD(12u, 0u);        
        status               = DEF_FAIL;
        p_dma_reg->IntErrClr = DEF_BIT(ch_nbr);
            
        callback_fnct(ch_nbr,
                      xfer_size_rem,
                      p_callback_arg,
                      status);
        
        int_err_stat = p_dma_reg->IntErrStat & DEF_BIT_FIELD(8u, 0u);                            
    }
}
Esempio n. 3
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CPU_BOOLEAN  CSP_DMA_CH_CfgExt (CSP_DEV_NBR   ch_nbr,
                                CSP_OPT       xfer_type,
                                CSP_OPT       src_burst_size,
                                CSP_OPT       src_width,
                                CSP_OPT       dest_burst_size,
                                CSP_OPT       dest_width,
                                CSP_DEV_NBR   src_req,
                                CSP_DEV_NBR   dest_req)
                                

{   CSP_DMA_REG     *p_dma_reg;
    CSP_DMA_CH_REG  *p_dma_ch_reg;
    CPU_INT32U       reg_cfg;
    CPU_INT32U       reg_ctrl;
    CPU_INT32U       reg_val;
    CPU_SR_ALLOC();
    
                                                                /* ------------------ ARGUMENTS CHECKING -------------- */
#if (CSP_CFG_ARG_CHK_EN == DEF_ENABLED)
    if (ch_nbr > CSP_DMA_CH_MAX_NBR - 1u) {                     /* Invalid channel number?                              */
        return (DEF_FAIL);
    }
                                                                /* Channel not available?                               */
    if (CSP_DMA_ChTbl[ch_nbr].State != CSP_DMA_CH_STATE_ALLOC) {
        return (DEF_FAIL);
    }
    
    if ((src_width != CPU_WORD_SIZE_08) &&                      /* Check src width parameter.                           */
        (src_width != CPU_WORD_SIZE_16) &&
        (src_width != CPU_WORD_SIZE_32)) {
        return (DEF_FAIL);
    }

    if ((dest_width != CPU_WORD_SIZE_08) &&                     /* Check src width parameter.                           */
        (dest_width != CPU_WORD_SIZE_16) &&
        (dest_width != CPU_WORD_SIZE_32)) {
        return (DEF_FAIL);
    }
#endif
                                                                /* Channel configuration.                               */
    reg_cfg  = DEF_BIT_NONE; 
    reg_ctrl = DEF_BIT_NONE;

    if (src_burst_size == 255u) {                               /* Set the source/destination burst size.               */
       reg_val   = 7u;
    } else if (src_burst_size >= 4u) {
        reg_val  = (DEF_INT_32_NBR_BITS - CPU_CntLeadZeros(src_burst_size) - 2u);        
    } else {
        reg_val  = DEF_BIT_NONE; 
    }
            
    DEF_BIT_SET(reg_ctrl, reg_val << 12u);

    if (dest_burst_size == 255u) {
       reg_val  = 7u;
    } else if (dest_burst_size >= 4u) {
        reg_val = (DEF_INT_32_NBR_BITS - CPU_CntLeadZeros(dest_burst_size) - 2u);        
    } else {
        reg_val = DEF_BIT_NONE;
    }

    DEF_BIT_SET(reg_ctrl, reg_val           << 15u);
    DEF_BIT_SET(reg_ctrl, (src_width  - 1u) << 18u);
    DEF_BIT_SET(reg_ctrl, (dest_width - 1u) << 21u);
    


                                                                /* Set the transfer type.                               */
    switch (xfer_type) {
        case CSP_DMA_XFER_TYPE_MEM_TO_PER:
             DEF_BIT_SET(reg_cfg, CSP_DMA_BIT_CH_CFG_XFER_MEM_TO_PER);              
             break;

        case CSP_DMA_XFER_TYPE_MEM_TO_MEM:
             DEF_BIT_SET(reg_cfg, CSP_DMA_BIT_CH_CFG_XFER_MEM_TO_MEM);              
             break;

        case CSP_DMA_XFER_TYPE_PER_TO_MEM:
             DEF_BIT_SET(reg_cfg, CSP_DMA_BIT_CH_CFG_XFER_PER_TO_MEM);              
             break;

        case CSP_DMA_XFER_TYPE_PER_TO_PER:
             DEF_BIT_SET(reg_cfg, CSP_DMA_BIT_CH_CFG_XFER_PER_TO_PER);
             break;
   
        default:
             return (DEF_FAIL);
    }
                                                                /* Configure source request signal  (see note #3)       */
                                                                /* ... transfer from peripheral?                        */
    if (((xfer_type == CSP_DMA_XFER_TYPE_PER_TO_MEM       )  || 
         (xfer_type == CSP_DMA_XFER_TYPE_PER_TO_PER       ))) {    
        
        if (src_req < CSP_DMA_XFER_PER_REQ_UART_00_TX) {
            ;    
        } else if (src_req < CSP_DMA_XFER_PER_REQ_TMR_00_MATCH_0) {
            CPU_CRITICAL_ENTER();
            DEF_BIT_CLR(CSP_DMA_REG_REQ_SEL, DEF_BIT(src_req - CSP_DMA_XFER_PER_REQ_UART_00_TX));
            CPU_CRITICAL_EXIT();
        } else {
            src_req -= CSP_DMA_XFER_PER_REQ_UART_00_TX;
   
            CPU_CRITICAL_ENTER();
            DEF_BIT_SET(CSP_DMA_REG_REQ_SEL, DEF_BIT(src_req - CSP_DMA_XFER_PER_REQ_UART_00_TX)); 
            CPU_CRITICAL_EXIT();
        }
        DEF_BIT_SET(reg_cfg, (src_req & CSP_DMA_MSK_CH_CFG_PER_REQ) << 1u);                
    }
    
    
    if (((xfer_type  == CSP_DMA_XFER_TYPE_MEM_TO_PER       )  || 
         (xfer_type  == CSP_DMA_XFER_TYPE_PER_TO_PER       ))) {

        if (dest_req < CSP_DMA_XFER_PER_REQ_UART_00_TX) {
            ;    
        } else if (dest_req < CSP_DMA_XFER_PER_REQ_TMR_00_MATCH_0) {
            CPU_CRITICAL_ENTER();
            DEF_BIT_CLR(CSP_DMA_REG_REQ_SEL, DEF_BIT(dest_req - CSP_DMA_XFER_PER_REQ_UART_00_TX));
            CPU_CRITICAL_EXIT();
        } else {
            dest_req -= CSP_DMA_XFER_PER_REQ_UART_00_TX;

            CPU_CRITICAL_ENTER();            
            DEF_BIT_SET(CSP_DMA_REG_REQ_SEL, DEF_BIT(dest_req - CSP_DMA_XFER_PER_REQ_UART_00_TX)); 
            CPU_CRITICAL_EXIT();
        }
             
        DEF_BIT_SET(reg_cfg, (dest_req & CSP_DMA_MSK_CH_CFG_PER_REQ) << 6u);        
    }

    p_dma_reg    = (CSP_DMA_REG *)CSP_ADDR_DMA_REG;                  
    p_dma_ch_reg = &(p_dma_reg->CHx[ch_nbr]);
    
    CPU_CRITICAL_ENTER();
    p_dma_ch_reg->Cfg      = (CPU_INT32U)reg_cfg;   
    p_dma_ch_reg->Ctrl     = (CPU_INT32U)reg_ctrl;       
    CPU_CRITICAL_EXIT();

    return (DEF_OK);
}