static CPU_SET_INFO( m6510 ) { switch (state) { default: CPU_SET_INFO_CALL(m6502); break; } }
/************************************************************************** * CPU-specific set_info **************************************************************************/ static CPU_SET_INFO( m68705 ) { m6805_Regs *cpustate = get_safe_token(device); switch(state) { /* --- the following bits of info are set as 64-bit signed integers --- */ case CPUINFO_INT_INPUT_STATE + M68705_INT_TIMER: m68705_set_irq_line(cpustate, M68705_INT_TIMER, info->i); break; default: CPU_SET_INFO_CALL(m6805); break; } }
static CPU_SET_INFO( m65c02 ) { m6502_Regs *cpustate = get_safe_token(device); switch (state) { /* --- the following bits of info are set as 64-bit signed integers --- */ case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: m65c02_set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break; default: CPU_SET_INFO_CALL(m6502); break; } }
/************************************************************************** * CPU-specific set_info for 68HC05EG **************************************************************************/ static CPU_SET_INFO( m68hc05eg ) { m6805_Regs *cpustate = get_safe_token(device); switch(state) { case CPUINFO_INT_INPUT_STATE + M68HC05EG_INT_IRQ: m68hc05eg_set_irq_line(cpustate, M68HC05EG_INT_IRQ, info->i); break; case CPUINFO_INT_INPUT_STATE + M68HC05EG_INT_TIMER: m68hc05eg_set_irq_line(cpustate, M68HC05EG_INT_TIMER, info->i); break; case CPUINFO_INT_INPUT_STATE + M68HC05EG_INT_CPI: m68hc05eg_set_irq_line(cpustate, M68HC05EG_INT_CPI, info->i); break; default: CPU_SET_INFO_CALL(m6805); break; } }
static CPU_SET_INFO( hd63705 ) { m6805_Regs *cpustate = get_safe_token(device); switch (state) { /* --- the following bits of info are set as 64-bit signed integers --- */ case CPUINFO_INT_INPUT_STATE + HD63705_INT_IRQ1: hd63705_set_irq_line(cpustate, HD63705_INT_IRQ1, info->i); break; case CPUINFO_INT_INPUT_STATE + HD63705_INT_IRQ2: hd63705_set_irq_line(cpustate, HD63705_INT_IRQ2, info->i); break; case CPUINFO_INT_INPUT_STATE + HD63705_INT_TIMER1: hd63705_set_irq_line(cpustate, HD63705_INT_TIMER1, info->i); break; case CPUINFO_INT_INPUT_STATE + HD63705_INT_TIMER2: hd63705_set_irq_line(cpustate, HD63705_INT_TIMER2, info->i); break; case CPUINFO_INT_INPUT_STATE + HD63705_INT_TIMER3: hd63705_set_irq_line(cpustate, HD63705_INT_TIMER3, info->i); break; case CPUINFO_INT_INPUT_STATE + HD63705_INT_PCI: hd63705_set_irq_line(cpustate, HD63705_INT_PCI, info->i); break; case CPUINFO_INT_INPUT_STATE + HD63705_INT_SCI: hd63705_set_irq_line(cpustate, HD63705_INT_SCI, info->i); break; case CPUINFO_INT_INPUT_STATE + HD63705_INT_ADCONV: hd63705_set_irq_line(cpustate, HD63705_INT_ADCONV, info->i); break; case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: hd63705_set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break; default: CPU_SET_INFO_CALL(m6805);break; } }