/* * csi2_ctx_config - CSI2 context configuration. * @ctx: context configuration * */ static void csi2_ctx_config(struct iss_csi2_device *csi2, struct iss_csi2_ctx_cfg *ctx) { u32 reg; /* Set up CSI2_CTx_CTRL1 */ if (ctx->eof_enabled) reg = CSI2_CTX_CTRL1_EOF_EN; if (ctx->eol_enabled) reg |= CSI2_CTX_CTRL1_EOL_EN; if (ctx->checksum_enabled) reg |= CSI2_CTX_CTRL1_CS_EN; iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL1(ctx->ctxnum), reg); /* Set up CSI2_CTx_CTRL2 */ reg = ctx->virtual_id << CSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT; reg |= ctx->format_id << CSI2_CTX_CTRL2_FORMAT_SHIFT; if (ctx->dpcm_decompress && ctx->dpcm_predictor) reg |= CSI2_CTX_CTRL2_DPCM_PRED; if (is_usr_def_mapping(ctx->format_id)) reg |= 2 << CSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT; iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL2(ctx->ctxnum), reg); /* Set up CSI2_CTx_CTRL3 */ iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL3(ctx->ctxnum), ctx->alpha << CSI2_CTX_CTRL3_ALPHA_SHIFT); /* Set up CSI2_CTx_DAT_OFST */ iss_reg_update(csi2->iss, csi2->regs1, CSI2_CTX_DAT_OFST(ctx->ctxnum), CSI2_CTX_DAT_OFST_MASK, ctx->data_offset); iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_PING_ADDR(ctx->ctxnum), ctx->ping_addr); iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_PONG_ADDR(ctx->ctxnum), ctx->pong_addr); }
/* * csi2_ctx_config - CSI2 context configuration. * @ctx: context configuration * */ static void csi2_ctx_config(struct iss_csi2_device *csi2, struct iss_csi2_ctx_cfg *ctx) { u32 reg; /* Set up CSI2_CTx_CTRL1 */ reg = readl(csi2->regs1 + CSI2_CTX_CTRL1(ctx->ctxnum)); if (ctx->eof_enabled) reg |= CSI2_CTX_CTRL1_EOF_EN; else reg &= ~CSI2_CTX_CTRL1_EOF_EN; if (ctx->eol_enabled) reg |= CSI2_CTX_CTRL1_EOL_EN; else reg &= ~CSI2_CTX_CTRL1_EOL_EN; if (ctx->checksum_enabled) reg |= CSI2_CTX_CTRL1_CS_EN; else reg &= ~CSI2_CTX_CTRL1_CS_EN; writel(reg, csi2->regs1 + CSI2_CTX_CTRL1(ctx->ctxnum)); /* Set up CSI2_CTx_CTRL2 */ reg = readl(csi2->regs1 + CSI2_CTX_CTRL2(ctx->ctxnum)); reg &= ~(CSI2_CTX_CTRL2_VIRTUAL_ID_MASK); reg |= ctx->virtual_id << CSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT; reg &= ~(CSI2_CTX_CTRL2_FORMAT_MASK); reg |= ctx->format_id << CSI2_CTX_CTRL2_FORMAT_SHIFT; if (ctx->dpcm_decompress) { if (ctx->dpcm_predictor) reg |= CSI2_CTX_CTRL2_DPCM_PRED; else reg &= ~CSI2_CTX_CTRL2_DPCM_PRED; } if (is_usr_def_mapping(ctx->format_id)) { reg &= ~CSI2_CTX_CTRL2_USER_DEF_MAP_MASK; reg |= 2 << CSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT; } writel(reg, csi2->regs1 + CSI2_CTX_CTRL2(ctx->ctxnum)); /* Set up CSI2_CTx_CTRL3 */ reg = readl(csi2->regs1 + CSI2_CTX_CTRL3(ctx->ctxnum)); reg &= ~(CSI2_CTX_CTRL3_ALPHA_MASK); reg |= (ctx->alpha << CSI2_CTX_CTRL3_ALPHA_SHIFT); writel(reg, csi2->regs1 + CSI2_CTX_CTRL3(ctx->ctxnum)); /* Set up CSI2_CTx_DAT_OFST */ reg = readl(csi2->regs1 + CSI2_CTX_DAT_OFST(ctx->ctxnum)); reg &= ~CSI2_CTX_DAT_OFST_MASK; reg |= ctx->data_offset; writel(reg, csi2->regs1 + CSI2_CTX_DAT_OFST(ctx->ctxnum)); writel(ctx->ping_addr, csi2->regs1 + CSI2_CTX_PING_ADDR(ctx->ctxnum)); writel(ctx->pong_addr, csi2->regs1 + CSI2_CTX_PONG_ADDR(ctx->ctxnum)); }