void stopTimer(CSL_TmrRegsOvly timer)
{
CSL_FINST(timer->TCR, TMR_TCR_ENAMODE12, DISABLED); //Stop TIM12
CSL_FINST(timer->TGCR, TMR_TGCR_TIM12RS, IN_RESET);
CSL_FINST(timer->TCR, TMR_TCR_ENAMODE34, DISABLED); //Stop TIM34
CSL_FINST(timer->TGCR, TMR_TGCR_TIM34RS, IN_RESET);
}
CSL_Status SAR_init (
void
)
{
volatile Uint16 i;
/* Enable the master clock in PCGCR Register */
CSL_FINST (CSL_SYSCTRL_REGS->PCGCR1,SYS_PCGCR1_SYSCLKDIS,ACTIVE );
/* Enable the Analog Register Clock Control module */
CSL_FINST (CSL_SYSCTRL_REGS->PCGCR2,SYS_PCGCR2_ANAREGCG, ACTIVE);
/* Enable SAR clock module */
CSL_FINST (CSL_SYSCTRL_REGS->PCGCR2, SYS_PCGCR2_SARCG, ACTIVE);
/* Reset SAR A/D Registers */
CSL_SAR_REGS->SARCTRL = CSL_ANACTRL_SARCTRL_RESETVAL
| CSL_ANACTRL_SARCTRL_CHSEL_MASK;
CSL_SAR_REGS->SARCLKCTRL = CSL_ANACTRL_SARCLKCTRL_RESETVAL
& CSL_ANACTRL_SARCLKCTRL_ADCCLKDIV_MASK;
CSL_SAR_REGS->SARPINCTRL = CSL_ANACTRL_SARPINCTRL_RESETVAL;
CSL_SAR_REGS->SARGPOCTRL = CSL_ANACTRL_SARGPOCTRL_RESETVAL;
/* provide delay after reset */
for(i=0;i<100;i++);
/* Configuring CLOCKOUT pin */
CSL_FINST (CSL_SYSCTRL_REGS->CCSSR, SYS_CCSSR_SRC, MODE9);
return CSL_SOK;
}
CSL_Status SAR_chanClose (
SAR_Handle hSar
)
{
hSar->chanNo = CSL_SAR_NO_CHAN;
if(NULL == hSar)
{
return CSL_ESYS_BADHANDLE;
}
// stop conversion
if(CSL_SAR_ADC_START ==
CSL_FEXT (hSar->baseAddr->SARCTRL,ANACTRL_SARCTRL_ADCSTRT) )
{
/* Stop SAR A/D conversion */
CSL_FINST (hSar->baseAddr->SARCTRL,ANACTRL_SARCTRL_ADCSTRT,
CLEAR);
}
/* Power Down the Analog */
CSL_FINST (hSar->baseAddr->SARPINCTRL,ANACTRL_SARPINCTRL_SARPWRUP,
CLEAR);
/* Power down the current bias circuit */
CSL_FINST (hSar->baseAddr->SARPINCTRL,ANACTRL_SARPINCTRL_PWRUPBIAS,
CLEAR);
hSar->baseAddr = NULL ;
hSar->status = CSL_SAR_CLOSE;
return CSL_SOK;
}
/**
* \brief CSL Audio Class main function
*
* \param None
*
* \return None
*/
void main(void)
{
CSL_Status status;
Uint32 gpioIoDir;
// Disable trace to reduce MHz load
//TRC_disable(TRC_GBLTARG);
/* Clock gate all peripherals */
CSL_SYSCTRL_REGS->PCGCR1 = 0x7FFF;
CSL_SYSCTRL_REGS->PCGCR2 = 0x007F;
#if defined(USE_I2S0_PB) || defined(USE_I2S0_REC)
/* SP0 Mode 1 (I2S0 and GP[5:4]) */
CSL_FINST(CSL_SYSCTRL_REGS->EBSR, SYS_EBSR_SP0MODE, MODE1);
#else
/* SP0 Mode 2 (GP[5:0]) -- GPIO02/GPIO04 for debug */
CSL_FINST(CSL_SYSCTRL_REGS->EBSR, SYS_EBSR_SP0MODE, MODE2);
#endif
#if defined(USE_I2S1_PB) || defined(USE_I2S1_REC)
/* SP1 Mode 1 (I2S1 and GP[11:10]) */
CSL_FINST(CSL_SYSCTRL_REGS->EBSR, SYS_EBSR_SP1MODE, MODE1);
#else
/* SP1 Mode 2 (GP[11:6]) */
CSL_FINST(CSL_SYSCTRL_REGS->EBSR, SYS_EBSR_SP1MODE, MODE2); /* need GPIO10 for AIC3204 reset */
#endif
/* PP Mode 1 (SPI, GPIO[17:12], UART, and I2S2) -- note this allows UART */
CSL_FINST(CSL_SYSCTRL_REGS->EBSR, SYS_EBSR_PPMODE, MODE1);
/* Reset C5515 -- ungates all peripherals */
C5515_reset();
/* Initialize DSP PLL */
status = pll_sample();
if (status != CSL_SOK)
{
LOG_printf(&trace, "ERROR: Unable to initialize PLL");
}
/* Clear pending timer interrupts */
CSL_SYSCTRL_REGS->TIAFR = 0x7;
#if !defined(USE_I2S0_PB) && !defined(USE_I2S0_REC)
/* GPIO02 and GPIO04 for debug */
/* GPIO10 for AIC3204 reset */
gpioIoDir = (((Uint32)CSL_GPIO_DIR_OUTPUT)<<CSL_GPIO_PIN2) |
(((Uint32)CSL_GPIO_DIR_OUTPUT)<<CSL_GPIO_PIN4) |
(((Uint32)CSL_GPIO_DIR_OUTPUT)<<CSL_GPIO_PIN10);
#else
/* GPIO10 for AIC3204 reset */
gpioIoDir = (((Uint32)CSL_GPIO_DIR_OUTPUT)<<CSL_GPIO_PIN10)
#endif
status = gpioInit(gpioIoDir, 0x00000000, 0x00000000);
if (status != GPIOCTRL_SOK)
{
LOG_printf(&trace, "ERROR: Unable to initialize GPIO");
}
/* Enable the USB LDO */
*(volatile ioport unsigned int *)(0x7004) |= 0x0001;
}
CSL_Status SAR_deInit(void)
{
/* Disable the Analog Register Clock Control module */
CSL_FINST (CSL_SYSCTRL_REGS->PCGCR2, SYS_PCGCR2_ANAREGCG, DISABLED);
/* Disable SAR clock module */
CSL_FINST (CSL_SYSCTRL_REGS->PCGCR2, SYS_PCGCR2_SARCG, DISABLED);
return CSL_SOK;
}
/** ===========================================================================
* @n@b LCD_init
*
* @b Description
* @n This is the initialization function for the LCD CSL. The function
* must be called before calling any other API from this CSL. This
* function is for enabling the clock to the LCD Controller.
* Currently, the function just return status CSL_SOK. as of now no
* checking is done inside the definition of function , but in near
* future it can be implemented.
*
* @b Arguments
* @verbatim
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Always returns
*
* <b> Pre Condition </b>
* @n This must be first API to use LCDC module.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_status status;
status = LCD_init();
@endverbatim
* ===========================================================================
*/
CSL_Status LCD_init(void)
{
/*enable the corresponding LCD clock from PCGCR Registers*/
CSL_FINST(CSL_SYSCTRL_REGS->PCGCR2, SYS_PCGCR2_LCDCG, ACTIVE);
/* set the reset clock cycle */
CSL_FINS(CSL_SYSCTRL_REGS->PSRCR,
SYS_PSRCR_COUNT, CSL_LCD_RESET_CLOCK_CYCLE);
CSL_FINST(CSL_SYSCTRL_REGS->PRCR, SYS_PRCR_PG4_RST, RST);
return CSL_SOK;
}
// Method to reset/reload the timer
void TMR_Reset(TimerID tID)
{
CSL_TmrRegsOvly tmrRegs = NULL;
// Get the base timer
switch (tID)
{
#if defined (OMAP_DSP) // Timers 0 & 1 belong to the DSP
case TMR_0_LOWER:
case TMR_0_UPPER:
tmrRegs = (CSL_TmrRegsOvly)CSL_TMR_0_REGS;
break;
case TMR_1_LOWER:
case TMR_1_UPPER:
tmrRegs = (CSL_TmrRegsOvly)CSL_TMR_1_REGS;
break;
#elif defined (OMAP_ARM) // Timers 2 & 3 belong to the ARM
case TMR_2_LOWER:
case TMR_2_UPPER:
tmrRegs = (CSL_TmrRegsOvly)CSL_TMR_2_REGS;
break;
case TMR_3_LOWER:
case TMR_3_UPPER:
tmrRegs = (CSL_TmrRegsOvly)CSL_TMR_3_REGS;
break;
#endif
default:
// Bad timer ID value passed in
DBG_LogUint16(DRIVER_DEBUG_ID, VERB_LEVEL1, "Attempted to Start Invalid Timer ID %d!", tID);
return;
}
// Put the timer in reset
CSL_FINST(tmrRegs->TGCR, TMR_TGCR_TIM12RS, RESET);
// Clear the timer value
if (tID < TMR_UPPER)
{
tmrRegs->TIM12 = 0;
}
else
{
tmrRegs->TIM34 = 0;
}
// Remove the reset and let the timer free run
CSL_FINST(tmrRegs->TGCR, TMR_TGCR_TIM12RS, NO_RESET);
}
void setupTimer64(CSL_TmrRegsOvly timer, Uint64 Period)
{
Uint32 prd12, prd34;
CSL_FINST(timer->TGCR, TMR_TGCR_TIMMODE, 64BIT_GPTIM); // Init GPTx in 64-bit mode
CSL_FINST(timer->TGCR, TMR_TGCR_TIM12RS, NOT_IN_RESET); // Remove GPTx TIM12 from Reset
CSL_FINST(timer->TGCR, TMR_TGCR_TIM34RS, NOT_IN_RESET); // Remove GPTx TIM34 from Reset (required in 64-bit)
prd12 = Period >> 32;
prd34 = Period;
CSL_FINS(timer->PRD12, TMR_PRD12_PRD12, prd12); // Load GPTx TIM1234 Period
CSL_FINS(timer->PRD34, TMR_PRD34_PRD34, prd34);
}
void resetTimer(CSL_TmrRegsOvly timer)
{
timer -> TCR = CSL_TMR_TCR_RESETVAL;
CSL_FINST(timer->TIM12, TMR_TIM12_CNT12, RESETVAL);
CSL_FINST(timer->TIM34, TMR_TIM34_CNT34, RESETVAL);
CSL_FINST(timer->PRD12, TMR_PRD12_PRD12, RESETVAL);
CSL_FINST(timer->PRD34, TMR_PRD34_PRD34, RESETVAL);
timer -> TGCR = CSL_TMR_TGCR_RESETVAL;
timer -> WDTCR = CSL_TMR_WDTCR_RESETVAL;
timer -> PID12 = (unsigned int)0x00010701C;//SL_TMR_PID12_RESETVAL;
timer -> EMUMGT_CLKSPD = CSL_TMR_EMUMGT_CLKSPD_RESETVAL;
timer -> GPTDAT_GPDIR = CSL_TMR_GPTDAT_GPDIR_RESETVAL;
timer -> GPINT_GPEN = CSL_TMR_GPINT_GPEN_RESETVAL;
}
/*
*
* aic3204_test( )
*
* Test different configurations of the AIC3204
*/
Int16 aic3204_test( )
{
/* Set A20_MODE for GPIO mode */
CSL_FINST(CSL_SYSCTRL_REGS->EBSR, SYS_EBSR_A20_MODE, MODE1);
/* Use GPIO to enable AIC3204 chip */
USBSTK5505_GPIO_init();
USBSTK5505_GPIO_setDirection(GPIO26, GPIO_OUT);
USBSTK5505_GPIO_setOutput( GPIO26, 1 ); // Take AIC3201 chip out of reset
/* Initialize I2C */
USBSTK5505_I2C_init( );
/* Codec tests */
printf( " -> 1 KHz Tone on Headphone.\n" );
if ( aic3204_tone_headphone( ) ) // Output test
return 1;
USBSTK5505_wait( 100 ); // Wait
printf( "<-> Audio Loopback from Stereo IN --> to HP OUT\n" );
if ( aic3204_loop_linein( ) ) // Loop test
return 3;
USBSTK5505_GPIO_setOutput( GPIO26, 0 ); // Disable AIC3204
return 0;
}
CSL_Status SAR_chanOpen (
CSL_SarHandleObj *SarObj,
CSL_SarChanSel chanSel
)
{
if(NULL == SarObj)
{
return CSL_ESYS_BADHANDLE;
}
if( chanSel < 0 || chanSel > CSL_SAR_CHAN_5 )
{
return CSL_ESYS_INVPARAMS;
}
/* Select the channel */
CSL_FINS (CSL_SAR_REGS->SARCTRL, ANACTRL_SARCTRL_CHSEL, chanSel);
/* Set multich discharge of array for every conversion*/
CSL_FINST (CSL_SAR_REGS->SARCTRL, ANACTRL_SARCTRL_MULTCH, SET);
SarObj->chanNo = chanSel;
SarObj->baseAddr = CSL_SAR_REGS;
SarObj->status = CSL_SAR_OPEN;
return CSL_SOK;
}
CSL_Status UART_setup(CSL_UartHandle hUart, CSL_UartSetup *uartSetup)
{
CSL_Status status =CSL_SOK;
Uint32 value;
Uint32 clk_div;
if( NULL == hUart )
{
return CSL_ESYS_BADHANDLE;
}
if( NULL == uartSetup)
{
return CSL_ESYS_INVPARAMS;
}
/**Putting UART recvor and xmittor in reset state*/
hUart->uartRegs->PWREMU_MGMT = CSL_UART_PWREMU_MGMT_RESETVAL;
/* Write 0 to DLAB to access IER*/
CSL_FINST(hUart->uartRegs->LCR, UART_LCR_DLAB, DLABON);
/*Disable all interrupts*/
hUart->uartRegs->IER = CSL_UART_IER_RESETVAL;
/* Flushing buffer */
value = (Uint32)(hUart->uartRegs->RBR);
/* reset and possibly enable FIFOs */
CSL_FINST(hUart->uartRegs->FCR, UART_FCR_FIFOEN, ENABLE);
CSL_FINST(hUart->uartRegs->FCR, UART_FCR_RXCLR, CLR);
CSL_FINST(hUart->uartRegs->FCR, UART_FCR_TXCLR, CLR);
hUart->uartRegs->FCR = uartSetup->fifoControl;
hUart->trigLevel = CSL_FEXT(uartSetup->fifoControl,UART_FCR_RXFIFTL);
clk_div = CSL_UART_CLK_DIVIDER(uartSetup->baud);
/* Set DLL and DLM to values appropriate for the required baudrate */
value = ( (Uint32) (uartSetup->clkInput) / (clk_div ) );
/* Write 1 to DLAB to access DLL and DLH*/
CSL_FINST(hUart->uartRegs->LCR, UART_LCR_DLAB, DLABOFF);
if ( ( (Uint32)(uartSetup->clkInput) % ( clk_div ) )
>= ( clk_div / 2 ) )
{
if ((value & 0xFF) != 0xFF)
{
hUart->uartRegs->DLL = (Uint8)(value & 0xFF) + 1;
hUart->uartRegs->DLH = (Uint8)((value & 0xFF00) >> 8);
}
else
{
int upp_start_transmit(
unsigned char *trans_buffer,
int receive_length,
int byte_receive_perline,
int send_length,
int byte_send_perline,unsigned char tranflag)
{
int status = 0;
int receive_line_cnt,send_line_cnt;
// unsigned short *xmtBuffer_pt;
#ifdef LoopBack
upp_fill_buffer(trans_buffer, dataWidth, UPP_DP_RJUST_0FILL, sendSize); // fill transmit buffer with test pattern
//
upp_fill_buffer(recv_buffer, 0, UPP_DP_RJUST_0FILL, receiveSize); // clear receive buffer
#else
receive_line_cnt=receive_length/byte_receive_perline;
send_line_cnt=send_length/byte_send_perline;
#endif
// Ensure uPP not enabled yet.
CSL_FINST(uppRegs->UPPCR, UPP_UPPCR_EN, DISABLE);
// init DMA channels
if(tranflag == 0)
{
while(CSL_FEXT(uppRegs->UPQS2, UPP_UPQS2_PEND) == 1);
upp_dma_prog(UPP_DMA_CHAN_Q, (void *)trans_buffer, receive_line_cnt, byte_receive_perline, byte_receive_perline);
}
if(tranflag == 1)
{
while(CSL_FEXT(uppRegs->UPIS2, UPP_UPIS2_PEND) == 1);
upp_dma_prog(UPP_DMA_CHAN_I, (void *)trans_buffer, send_line_cnt, byte_send_perline, byte_send_perline);
}
// Enable uPP here. PCR.EN bit
CSL_FINST(uppRegs->UPPCR, UPP_UPPCR_EN, ENABLE);
status = 0;
upp_test_exit:
return status;
}
/* SampleBySample
* copy of CSL I2S_transEnable function to work with DDC_I2SObj type handle
***********************************************************************/
void DDC_I2S_transEnable(DDC_I2SHandle hI2s, Uint16 enableBit)
{
ioport CSL_I2sDrvRegs *localregs;
localregs = hI2s->regs;
//localregs->SCRL = 0x2A00;
if(enableBit == TRUE)
{
/* Enable the transmit and receive bit */
CSL_FINST(localregs->SCRL, I2S_I2SSCTRL_ENABLE, SET);
}
else
{
/* Disable the transmit and receive bit */
CSL_FINST(localregs->SCRL, I2S_I2SSCTRL_ENABLE, CLEAR);
}
}
/** ============================================================================
* @n@b PLL_bypass
*
* @b Description
* @n This API is used to Bypass the PLL.
*
* @b Arguments
* @verbatim
hPll Handle to the pll
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Bypassing the PLL is successful
*
* @li CSL_ESYS_BADHANDLE - The handle passed is invalid
*
* <b> Pre Condition </b>
* @n PLL_init and PLL_config should be called successfully.
*
* <b> Post Condition </b>
* @n Pll is bypassed
*
* @b Modifies
* @n hPll variable
*
* @b Example
* @verbatim
CSL_Status status;
PLL_Obj pllObj;
PLL_Config configInfo;
PLL_Handle hPll;
Uint32 pllInstId;
pllInstId = 0;
status = PLL_init(&pllObj,pllInstId);
hPll = &pllObj;
.......
Configure the PLL for 12.288MHz
configInfo.PLLCNTL1 = 0x82ed;
configInfo.PLLINCNTL = 0x8000;
configInfo.PLLCNTL2 = 0x0806;
configInfo.PLLOUTCNTL = 0x0200;
status = PLL_config(hPll, &configInfo);
status = PLL_bypass(hPll);
@endverbatim
* ============================================================================
*/
CSL_Status PLL_bypass(PLL_Handle hPll)
{
CSL_Status status;
status = CSL_SOK;
if(NULL == hPll)
{
status = CSL_ESYS_BADHANDLE;
return status;
}
/* Bypass the PLL */
CSL_FINST(hPll->sysAddr->CCR2, SYS_CCR2_SYSCLKSEL, BYPASS);
CSL_FINST(hPll->sysAddr->CGCR1, SYS_CGCR1_PLL_PWRDN, POWERDWN);
return (status);
}
CSL_Status UART_init(CSL_UartObj * uartObj,Uint32 uartInstId,
CSL_UartOpmode opmode)
{
CSL_Status status = CSL_SOK;
if(NULL == uartObj)
{
return CSL_ESYS_INVPARAMS;
}
if(opmode == UART_OPMODE_OTHER)
{
return CSL_ESYS_INVPARAMS;
}
/* Set the base address */
switch ( uartInstId)
{
case CSL_UART_INST_0:
uartObj->insId = uartInstId;
uartObj->sysAddr = CSL_SYSCTRL_REGS;
uartObj->uartRegs = CSL_UART_REGS;
uartObj->opmode = opmode;
break;
default:
uartObj->insId = CSL_UART_INST_INVALID;
status = CSL_EUART_INVALID_INST_ID;
break;
}
if(CSL_UART_INST_INVALID != uartObj->insId)
{
/**Enable Master clock */
CSL_FINST(uartObj->sysAddr->PCGCR1,SYS_PCGCR1_SYSCLKDIS,ACTIVE);
/**Enable uart peripheral clock gating */
CSL_FINST(uartObj->sysAddr->PCGCR1,SYS_PCGCR1_UARTCG,ACTIVE);
/* changing parallel port mode to 5 - supports UART */
CSL_FINST(uartObj->sysAddr->EBSR,SYS_EBSR_PPMODE,MODE5);
/**Resetting UART module*/
CSL_FINST(uartObj->sysAddr->PRCR, SYS_PRCR_PG4_RST,RST);
}
return status;
}
CSL_Status SAR_startConversion (
SAR_Handle hSar
)
{
if(NULL == hSar)
{
return CSL_ESYS_BADHANDLE;
}
/* Start SAR A/D conversion */
CSL_FINST (hSar->baseAddr->SARCTRL, ANACTRL_SARCTRL_ADCSTRT, SET);
return CSL_SOK;
}
static void LOCAL_exampleInit(Uint8 pruNum)
{
Uint32 i;
Uint32 *pruDataMem;
// Turn on the EDMA CC and TCs
DEVICE_LPSCTransition(CSL_PSC_0, CSL_PSC_CC0, 0, CSL_PSC_MDCTL_NEXT_ENABLE);
DEVICE_LPSCTransition(CSL_PSC_0, CSL_PSC_TC0, 0, CSL_PSC_MDCTL_NEXT_ENABLE);
DEVICE_LPSCTransition(CSL_PSC_0, CSL_PSC_TC1, 0, CSL_PSC_MDCTL_NEXT_ENABLE);
// Initialize memory pointer
if (pruNum == 0)
{
pruDataMem = (Uint32 *) PRU0_DATA_RAM_START;
}
else if (pruNum == 1)
{
pruDataMem = (Uint32 *) PRU1_DATA_RAM_START;
}
// Put src and dst addresses into PRU data memory so PRU code can read them
pruDataMem[0] = (Uint32) srcBuf;
pruDataMem[1] = (Uint32) dstBuf;
// Init src and dst buffers
for (i = 0; i < sizeof(srcBuf); i++)
{
srcBuf[i] = rand() & 0xFF;
dstBuf[i] = 0;
}
// Clear EDMA CC0 interrupt
CSL_FINST(intcRegs->EVTCLR[0], DSPINTC_EVTCLR_EC8, SET);
// Connect the EDMA CC0 event to the DSP interrupt 12
CSL_FINS(intcRegs->INTMUX3, DSPINTC_INTMUX3_INTSEL12, EDMA3_CC0_INT1);
// Set ISTP to point to the vector table address
ISTP = (Uint32)intcVectorTable;
// Clear all interrupts, bits 4 thru 15
ICR = 0xFFF0;
// Enable the bits for non maskable interrupt 12 and NMIE
IER = 0x1002;
// Enable interrupts, set GIE bit
_enable_interrupts();
}
/** ============================================================================
* @n@b I2C_init
*
* @b Description
* @n Initializes the I2C CSL module
*
* @b Arguments
* @verbatim
instanceNum I2C Hardware instance number
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Returned for success
* @li CSL_ESYS_INVPARAMS - Invalid parameter
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Initializes I2C module
*
* @b Modifies
* @n I2C Object structure
*
* @b Example
* @verbatim
CSL_Status status;
status = I2C_init(CSL_I2C0);
@endverbatim
* ============================================================================
*/
CSL_Status I2C_init(Uint16 instanceNum)
{
CSL_Status status;
volatile Uint16 looper;
status = CSL_SOK;
switch(instanceNum)
{
case CSL_I2C0 :
i2cHandle = &gI2cObj[CSL_I2C0];
i2cHandle->i2cRegs = CSL_I2C_0_REGS;
i2cHandle->sysCtrlRegs = CSL_SYSCTRL_REGS;
/* Enable I2C module in Idle PCGCR */
CSL_FINST(i2cHandle->sysCtrlRegs->PCGCR1,
SYS_PCGCR1_I2CCG, ACTIVE);
/* Reset I2C module */
CSL_FINS(i2cHandle->sysCtrlRegs->PSRCR, SYS_PSRCR_COUNT,
CSL_I2C_RESET_COUNT_VAL);
CSL_FINST(i2cHandle->sysCtrlRegs->PRCR, SYS_PRCR_I2C_RST, RST);
/* Give some delay for the device to reset */
for(looper = 0; looper < CSL_I2C_RESET_DELAY; looper++)
{;}
break;
default :
status = CSL_ESYS_INVPARAMS;
break;
}
return(status);
}
CSL_Status PLL_enable(PLL_Handle hPll)
{
CSL_Status status;
Uint16 timeout;
status = CSL_SOK;
timeout = TIMEOUT;
if(NULL == hPll)
{
status = CSL_ESYS_BADHANDLE;
return (status);
}
/* Enable the PLL */
CSL_FINST(hPll->sysAddr->CGCR1, SYS_CGCR1_PLL_PWRDN, POWERED);
while (!PLL_getTestLockMonStatus(hPll) && timeout--) ;
/* Select pll */
CSL_FINST(hPll->sysAddr->CCR2, SYS_CCR2_SYSCLKSEL, LOCK);
return (status);
}
CSL_Status PLL_config(PLL_Handle hPll,
PLL_Config *pconfigInfo)
{
Uint16 timeout = TIMEOUT;
CSL_Status status = CSL_SOK;
if(NULL == hPll)
{
status = CSL_ESYS_BADHANDLE;
return status;
}
if(NULL == pconfigInfo)
{
status = CSL_ESYS_INVPARAMS;
return status;
}
hPll->pllConfig = pconfigInfo;
/* Force to BYPASS mode */
CSL_FINST(hPll->sysAddr->CCR2, SYS_CCR2_SYSCLKSEL, BYPASS);
/* Set CLR_CTRL = 0 in CGCR1 */
CSL_FINST(hPll->sysAddr->CGCR1, SYS_CGCR1_CLR_CNTL, CLEAR);
hPll->sysAddr->CGICR = pconfigInfo->PLLINCNTL;
hPll->sysAddr->CGOCR = pconfigInfo->PLLOUTCNTL;
hPll->sysAddr->CGCR2 = pconfigInfo->PLLCNTL2;
/*
* Set PLL_PWRDN = 0, PLL_STANDBY = 0, CLR_CNTL = 1 and program MH in CGCR1
* according to your required settings
*/
CSL_FINST(hPll->sysAddr->CGCR1, SYS_CGCR1_PLL_PWRDN, POWERED);
CSL_FINST(hPll->sysAddr->CGCR1, SYS_CGCR1_PLL_STANDBY, ACTIVE);
CSL_FINST(hPll->sysAddr->CGCR1, SYS_CGCR1_CLR_CNTL, SET);
#if (defined(CHIP_C5505_C5515) || defined(CHIP_C5504_C5514))
hPll->sysAddr->CGCR1 |= ((CSL_SYS_CGCR1_VP_MASK | CSL_SYS_CGCR1_VS_MASK) &
pconfigInfo->PLLCNTL1);
#else
hPll->sysAddr->CGCR1 |= (CSL_SYS_CGCR1_MH_MASK & pconfigInfo->PLLCNTL1);
#endif
while (!PLL_getTestLockMonStatus(hPll) && timeout--) ;
/* Select pll */
CSL_FINST(hPll->sysAddr->CCR2, SYS_CCR2_SYSCLKSEL, LOCK);
return (status);
}
/** ============================================================================
* @n@b I2C_eventDisable
*
* @b Description
* @n Disables the I2C events.
* I2C has several events which can generate interrupt to the CPU.
* Application can disable any of the event using this function.
*
* @b Arguments
* @verbatim
i2cEvent Event to be disabled
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Returned for success
* @li CSL_ESYS_INVPARAMS - Invalid parameter
*
* <b> Pre Condition </b>
* @n I2C_init and I2C_eventEnable should be called successfully
*
* <b> Post Condition </b>
* @n Disables I2C interrupt for a particular event
*
* @b Modifies
* @n I2C Interrupt enable register
*
* @b Example
* @verbatim
CSL_Status status;
status = I2C_init(CSL_I2C0);
....
....
status = I2C_eventEnable(CSL_I2C_EVENT_ICXRDY);
....
....
status = I2C_eventDisable(CSL_I2C_EVENT_ICXRDY);
@endverbatim
* ============================================================================
*/
CSL_Status I2C_eventDisable(CSL_I2cEvent i2cEvent)
{
CSL_Status status;
status = CSL_SOK;
switch(i2cEvent)
{
/* Disable Arbitration loss Event */
case CSL_I2C_EVENT_AL:
CSL_FINST(i2cHandle->i2cRegs->ICIMR, I2C_ICIMR_AL, DISABLE);
break;
/* Disable No acknowledgement Event */
case CSL_I2C_EVENT_NACK:
CSL_FINST(i2cHandle->i2cRegs->ICIMR, I2C_ICIMR_NACK, DISABLE);
break;
/* Disable Access ready Event */
case CSL_I2C_EVENT_ARDY:
CSL_FINST(i2cHandle->i2cRegs->ICIMR, I2C_ICIMR_ARDY, DISABLE);
break;
/* Disable Receive ready Event */
case CSL_I2C_EVENT_ICRRDY:
CSL_FINST(i2cHandle->i2cRegs->ICIMR, I2C_ICIMR_ICRRDY, DISABLE);
break;
/* Disable Transmit ready Event */
case CSL_I2C_EVENT_ICXRDY:
CSL_FINST(i2cHandle->i2cRegs->ICIMR, I2C_ICIMR_ICXRDY, DISABLE);
break;
/* Disable Stop condition detected Event */
case CSL_I2C_EVENT_SCD:
CSL_FINST(i2cHandle->i2cRegs->ICIMR, I2C_ICIMR_SCD, DISABLE);
break;
/* Disable Address as slave Event */
case CSL_I2C_EVENT_AAS:
CSL_FINST(i2cHandle->i2cRegs->ICIMR, I2C_ICIMR_AAS, DISABLE);
break;
default :
status = CSL_ESYS_INVPARAMS;
break;
}
return(status);
}
/*
* Init_SAR(void)
* Initialize SAR ADC
*
* Returns
* 0 : Success
* 1 : Fail
*/
void EZDSP5535_SAR_init(void)
{
/* Initialize the SAR module */
/* Reset SAR A/D Registers */
CSL_SAR_REGS->SARCTRL = CSL_ANACTRL_SARCTRL_RESETVAL
| CSL_ANACTRL_SARCTRL_CHSEL_MASK;
CSL_SAR_REGS->SARCLKCTRL = CSL_ANACTRL_SARCLKCTRL_RESETVAL
& CSL_ANACTRL_SARCLKCTRL_ADCCLKDIV_MASK;
CSL_SAR_REGS->SARPINCTRL = CSL_ANACTRL_SARPINCTRL_RESETVAL;
CSL_SAR_REGS->SARGPOCTRL = CSL_ANACTRL_SARGPOCTRL_RESETVAL;
/* provide delay after reset */
EZDSP5535_waitusec(10);
/* Configuring CLOCKOUT pin */
CSL_FINST (CSL_SYSCTRL_REGS->CCSSR, SYS_CCSSR_SRC, MODE9);
/* Open SAR channel 3 */
/* Set multich discharge of array for every conversion*/
CSL_SAR_REGS->SARCTRL = (3 << 12) | (0<<11);
/* Reset the SAR clock control Register */
CSL_SAR_REGS->SARCLKCTRL = CSL_ANACTRL_SARCLKCTRL_RESETVAL;
/* Configuring ClkDivider value */
CSL_SAR_REGS->SARCLKCTRL = 0x0b;
/* Enabling PwrUp SAR A/D module */
CSL_SAR_REGS->SARPINCTRL = 0x0000 /* status mask bit14 */
| 0x2000 /* powerup bias */
| 0x1000 /* powerup */
| 0x0000 /* disable reference buffer, bit10*/
| 0x0000 /* bandgap ref to 0.8v, bit9 */
| 0x0100 /* set Reference volatge to VDD_SAR */
| 0x0000 /* disable AVddMwas, bit3 */
| 0x0000 /* not ground analog ch0, bit1 */
| 0x0000; /* A/D is based on Vin. bit0 */
// CSL_SAR_REGS->SARCTRL &= ~(1<<11); /* continuous conversion */
/* Start the continuous conversion */
CSL_SAR_REGS->SARCTRL |= 0x8000;
}
CSL_Status SAR_stopConversion (
SAR_Handle hSar
)
{
if(NULL == hSar)
{
return CSL_ESYS_BADHANDLE;
}
/* Check whether conversion start bit is set or not */
if(CSL_SAR_ADC_START ==
CSL_FEXT (hSar->baseAddr->SARCTRL, ANACTRL_SARCTRL_ADCSTRT) )
{
/* Stop SAR A/D conversion */
CSL_FINST (hSar->baseAddr->SARCTRL, ANACTRL_SARCTRL_ADCSTRT, CLEAR);
}
return CSL_SOK;
}
/** ============================================================================
* @n@b PLL_reset
*
* @b Description
* @n Resets all the PLL registers.
*
* @b Arguments
* @verbatim
hPll Handle to the pll
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Resetting the PLL is successful.
*
* @li CSL_ESYS_BADHANDLE - The handle passed is invalid
*
*
* <b> Pre Condition </b>
* @n PLL_init should be called successfully.
*
* <b> Post Condition </b>
* @n PLL registers are resetted.
*
* @b Modifies
* @n hPll variable
*
* @b Example
* @verbatim
CSL_Status status;
PLL_Obj pllObj;
Uint32 pllInstId;
PLL_Handle hPll;
pllInstId = 0;
status = PLL_init(&pllObj,pllInstId);
.....
hPll = &pllObj;
status = PLL_reset(hPll);
@endverbatim
* ============================================================================
*/
CSL_Status PLL_reset(PLL_Handle hPll)
{
CSL_Status status;
status = CSL_SOK;
if(NULL == hPll)
{
status = CSL_ESYS_BADHANDLE;
return (status);
}
/* Bypass the PLL */
CSL_FINST(hPll->sysAddr->CCR2, SYS_CCR2_SYSCLKSEL, BYPASS);
/* Reset PLL register */
hPll->sysAddr->CGCR1 = CSL_SYS_CGCR1_RESETVAL;
hPll->sysAddr->CGICR = CSL_SYS_CGICR_RESETVAL;
hPll->sysAddr->CGOCR = CSL_SYS_CGOCR_RESETVAL;
hPll->sysAddr->CGCR2 = CSL_SYS_CGCR2_RESETVAL;
return (status);
}
/*
* Interrupt service routines
*/
interrupt void EDMA3_CC0_INT1_isr()
{
edmaIntReceived = 1;
CSL_FINST(intcRegs->EVTCLR[0], DSPINTC_EVTCLR_EC8, SET);
}
/** ============================================================================
* @n@b I2C_setup
*
* @b Description
* @n Sets the I2C hardware registers.
* This functions task is same as that of I2C_config, but this function
* provides more flexible interface to the application. Application can
* pass the individual configuration values rather than the register value.
*
* @b Arguments
* @verbatim
i2cSetup I2C setup structure
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Returned for success
* @li CSL_ESYS_INVPARAMS - Invalid parameter
*
* <b> Pre Condition </b>
* @n I2C_init should be called successfully
*
* <b> Post Condition </b>
* @n Sets the I2C register values
*
* @b Modifies
* @n I2C registers
*
* @b Example
* @verbatim
#define CSL_I2C_SYS_CLK (12) // In MHz
#define CSL_I2C_BUS_FREQ (10) // In KHz
CSL_Status status;
CSL_I2cSetup i2cSetup;
i2cSetup.addrMode = CSL_I2C_ADDR_7BIT;
i2cSetup.bitCount = CSL_I2C_BC_8BITS;
i2cSetup.loopBack = CSL_I2C_LOOPBACK_DISABLE;
i2cSetup.freeMode = CSL_I2C_FREEMODE_DISABLE;
i2cSetup.repeatMode = CSL_I2C_REPEATMODE_DISABLE;
i2cSetup.ownAddr = CSL_I2C_OWN_ADDR;
i2cSetup.sysInputClk = CSL_I2C_SYS_CLK;
i2cSetup.i2cBusFreq = CSL_I2C_BUS_FREQ;
status = I2C_init(CSL_I2C0);
....
status = I2C_setup(&i2cSetup);
@endverbatim
* ============================================================================
*/
CSL_Status I2C_setup(CSL_I2cSetup *i2cSetup)
{
Uint16 pscValue;
Uint16 clock;
Uint16 d;
if(i2cSetup != NULL)
{
/* Set I2C address mode */
CSL_FINS(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_XA, i2cSetup->addrMode);
/* Set I2C Bit count value */
CSL_FINS(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_BC, i2cSetup->bitCount);
/* Enable/Disable loopback mode */
CSL_FINS(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_DLB, i2cSetup->loopBack);
/* Enable/Disable free running mode */
CSL_FINS(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_FREE,
i2cSetup->freeMode);
/* Enable/Disable repeat mode */
CSL_FINS(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_RM,
i2cSetup->repeatMode);
/* Set the I2C own address */
CSL_FINS(i2cHandle->i2cRegs->ICOAR, I2C_ICOAR_OADDR,
i2cSetup->ownAddr);
/* calculating the IPSC value */
pscValue = (i2cSetup->sysInputClk) / CSL_I2C_MODULE_CLOCK_FREQ;
/* Adjust the Prescaler value */
if(pscValue > (i2cSetup->sysInputClk % CSL_I2C_MODULE_CLOCK_FREQ))
{
pscValue -= CSL_I2C_PSC_ADJUST_VAL;
}
if(pscValue == CSL_I2C_PSC0)
{
d = CSL_I2C_PSC0_DVAL;
}
else if(pscValue == CSL_I2C_PSC1)
{
d = CSL_I2C_PSC1_DVAL;
}
else
{
d = CSL_I2C_PSC2TOFF_DVAL;
}
CSL_FINS(i2cHandle->i2cRegs->ICPSC, I2C_ICPSC_IPSC, pscValue);
/* calculating the ICCLKL and ICCLKH register values */
clock = (((i2cSetup->sysInputClk * CSL_I2C_CLK_MULT * CSL_I2C_CLK_MULT) / \
((pscValue + CSL_I2C_PSC_ADJUST_VAL) * i2cSetup->i2cBusFreq * \
CSL_I2C_CLK_MULT * 2u)) - (d)) ;
/* Configure clock low register */
CSL_FINS(i2cHandle->i2cRegs->ICCLKL, I2C_ICCLKL_ICCL, clock);
/* Configure clock high register */
CSL_FINS(i2cHandle->i2cRegs->ICCLKH, I2C_ICCLKH_ICCH, clock);
/* Bring the I2C out of reset */
CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_IRS, SET);
}
else
{
return(CSL_ESYS_INVPARAMS);
}
return(CSL_SOK);
}
/** ===========================================================================
* @n@b LCD_setup
*
* @b Description
* @n It configures the LCDC register specific to LIDD controller to draw
* the images or text on LCD panel.
*
* @b Arguments
* @verbatim
hLcdc Handle to the LCDC.
setup Pointer to LCDC setup structure.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Hardware setup successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVPARAMS - setup Parameter is invalid.
*
* <b> Pre Condition </b>
* @n LCD_open() API should be called before this.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n LCDC Registers will be populated.
*
* @b Example
* @verbatim
Uint16 instanceNum;
CSL_status status;
CSL_LcdcObj pLcdcObj
CSL_LcdcHandle hLcdc;
CSL_LcdcHwSetup setup;
...
CSL_LcdcConfigLidd configLIDD;
CSL_LcdcLiddTiming timingCs0LIDD;
CSL_LcdcLiddTiming timingCs1LIDD;
.........\\\\\\\\\\\\\ SETUP for LIDD Controller
configLIDD.clkDiv = 0x3;
configLIDD.fdoneIntEn = CSL_LCDC_LIDD_FDONE_DISABLE ;
configLIDD.dmaCs0Cs1 = CSL_LCDC_LIDD_CS0;
configLIDD.dmaEnable = CSL_LCDC_LIDD_DMA_DISABLE;
configLIDD.polControl = 0x0000;
configLIDD.modeSel = CSL_LCDC_LIDD_ASYNC_MPU80;
timingCs0LIDD.wSu = 0x1F;
timingCs0LIDD.wStrobe = 0x3F ;
timingCs0LIDD.wHold = 0x0F;
timingCs0LIDD.rSu = 0x1F;
timingCs0LIDD.rStrobe = 0x3F;
timingCs0LIDD.rHold = 0x0F;
timingCs0LIDD.ta = 0x01;
timingCs1LIDD.wSu = 0x1F;
timingCs1LIDD.wStrobe = 0x3F ;
timingCs1LIDD.wHold = 0x0F;
timingCs1LIDD.rSu = 0x1F;
timingCs1LIDD.rStrobe = 0x3F;
timingCs1LIDD.rHold = 0x0F;
timingCs1LIDD.ta = 0x01;
setup.config = configLIDD;
setup.useCs1 = CSL_LCDC_LIDD_NOT_USE_CS1;
setup.timingCs0 = timingCs0LIDD;
setup.extendSetup = NULL;
||||||||||||*******************************************************||||||||||||
instanceNum = CSL_LCDC_INSTANCE_0
hLcdc = LCD_open(instanceNum, &pLcdcObj, &status);
status = LCD_setup(hLcdc, &setup);
...
@endverbatim
* ===========================================================================
*/
CSL_Status LCD_setup (
CSL_LcdcHandle hLcdc,
CSL_LcdcHwSetup* setup )
{
Uint16 tempVar;
if((hLcdc != NULL) && (setup != NULL))
{
/* passed parameters are ok */
}
else
{
if(hLcdc == NULL)
{
return CSL_ESYS_BADHANDLE;
}
else
{
return CSL_ESYS_INVPARAMS;
}
}
/* clear the all data of the status register */
CSL_FINS(hLcdc->regs->LCDSR, LCDC_LCDSR_EOF1, CSL_LCD_ENABLE);
CSL_FINS(hLcdc->regs->LCDSR, LCDC_LCDSR_EOF0, CSL_LCD_ENABLE);
CSL_FINS(hLcdc->regs->LCDSR, LCDC_LCDSR_PL, CSL_LCD_ENABLE);
CSL_FINS(hLcdc->regs->LCDSR, LCDC_LCDSR_FUF, CSL_LCD_ENABLE);
CSL_FINS(hLcdc->regs->LCDSR, LCDC_LCDSR_ABC, CSL_LCD_ENABLE);
CSL_FINS(hLcdc->regs->LCDSR, LCDC_LCDSR_SYNC, CSL_LCD_ENABLE);
CSL_FINS(hLcdc->regs->LCDSR, LCDC_LCDSR_DONE, CSL_LCD_ENABLE);
/* set the lcd controller mode to LIDD */
CSL_FINST (hLcdc->regs->LCDCR, LCDC_LCDCR_MODESEL, LIDD);
/* configure the registers required for LIDD controller */
/* CSL_FINST (hLcdc->regs->LCDRASTCR0,
LCDC_LCDRASTCR0_LCDEN, DISABLE); */
/* configure LIDD control register */
tempVar = (setup->config).polControl;
CSL_FINS (hLcdc->regs->LCDLIDDCR, LCDC_LCDLIDDCR_DONE_INT_EN,
(setup->config).fdoneIntEn);
CSL_FINS (hLcdc->regs->LCDLIDDCR, LCDC_LCDLIDDCR_LIDD_MODE_SEL,
(setup->config).modeSel);
CSL_FINS (hLcdc->regs->LCDCR, LCDC_LCDCR_CLKDIV,
(setup->config).clkDiv);
CSL_FINS (hLcdc->regs->LCDLIDDCR, LCDC_LCDLIDDCR_DMA_CS0_CS1,
(setup->config).dmaCs0Cs1);
hLcdc->regs->LCDLIDDCR &= ~CSL_LCDC_LCDLIDDCR_CS1_E1_POL_MASK;
hLcdc->regs->LCDLIDDCR &= ~CSL_LCDC_LCDLIDDCR_CS0_E0_POL_MASK;
hLcdc->regs->LCDLIDDCR &= ~CSL_LCDC_LCDLIDDCR_WS_DIR_POL_MASK;
hLcdc->regs->LCDLIDDCR &= ~CSL_LCDC_LCDLIDDCR_RS_EN_POL_MASK;
hLcdc->regs->LCDLIDDCR &= ~CSL_LCDC_LCDLIDDCR_ALEPOL_MASK;
hLcdc->regs->LCDLIDDCR |=
(tempVar << CSL_LCDC_LCDLIDDCR_ALEPOL_SHIFT);
CSL_FINS (hLcdc->regs->LCDLIDDCR, LCDC_LCDLIDDCR_LIDD_DMA_EN,
(setup->config).dmaEnable);
/* configure LIDD chip selct configuration register */
if(CSL_LCDC_LIDD_NOT_USE_CS1 == (setup->useCs1))
{
/* configure LIDD CS0 configuration register */
tempVar = (setup->timingCs0).rSu;
CSL_FINS (hLcdc->regs->LCDLIDDCS0CONFIG0,
LCDC_LCDLIDDCS0CONFIG0_R_STROBE,
(setup->timingCs0).rStrobe);
CSL_FINS (hLcdc->regs->LCDLIDDCS0CONFIG0,
LCDC_LCDLIDDCS0CONFIG0_R_HOLD,
(setup->timingCs0).rHold);
CSL_FINS (hLcdc->regs->LCDLIDDCS0CONFIG0,
LCDC_LCDLIDDCS0CONFIG0_TA,
(setup->timingCs0).ta);
if(tempVar >= 16)
{
tempVar = tempVar - 15 ;
tempVar = tempVar >> 4;
hLcdc->regs->LCDLIDDCS0CONFIG0 |=
CSL_LCDC_LCDLIDDCS0CONFIG0_R_SU0_MASK;
CSL_FINS (hLcdc->regs->LCDLIDDCS0CONFIG1,
LCDC_LCDLIDDCS0CONFIG1_R_SU1, tempVar);
}
/** ============================================================================
* @n@b I2C_write
*
* @b Description
* @n Transmits the I2C data to I2C device.
*
* @b Arguments
* @verbatim
i2cWrBuf I2C Data buffer pointer
dataLength Number bytes to transmit
slaveAddr Address of the slave device
masterMode Master mode flag
startStopFlag Flag for the start and stop bits
timeout Time out variable
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Returned for success
* @li CSL_ESYS_INVPARAMS - Invalid parameter
* @li CSL_I2C_BUS_BUSY_ERR - Busy Bit Error
* @li CSL_I2C_TIMEOUT_ERROR - Time out Error has occured
* @li CSL_I2C_NACK_ERR - No acknowledgement Error
*
* <b> Pre Condition </b>
* @n I2C_init and I2C_config/I2C_setup should be called successfully
*
* <b> Post Condition </b>
* @n Transmits the I2C data
*
* @b Modifies
* @n I2C transmit register
*
* @b Example
* @verbatim
#define CSL_I2C_SYS_CLK (12) // In MHz
#define CSL_I2C_BUS_FREQ (10) // In KHz
#define CSL_I2C_DATA_SIZE (16)
#define CSL_I2C_EEPROM_ADDR (0x50)
Uint16 i2cDataBuf[CSL_I2C_DATA_SIZE];
CSL_Status status;
CSL_I2cSetup i2cSetup;
i2cSetup.addrMode = CSL_I2C_ADDR_7BIT;
i2cSetup.bitCount = CSL_I2C_BC_8BITS;
i2cSetup.loopBack = CSL_I2C_LOOPBACK_DISABLE;
i2cSetup.freeMode = CSL_I2C_FREEMODE_DISABLE;
i2cSetup.repeatMode = CSL_I2C_REPEATMODE_DISABLE;
i2cSetup.ownAddr = CSL_I2C_OWN_ADDR;
i2cSetup.sysInputClk = CSL_I2C_SYS_CLK;
i2cSetup.i2cBusFreq = CSL_I2C_BUS_FREQ;
status = I2C_init(CSL_I2C0);
....
status = I2C_setup(&i2cSetup);
....
....
status = I2C_write(i2cDataBuf, CSL_I2C_DATA_SIZE,
CSL_I2C_EEPROM_ADDR, TRUE, 1,
CSL_I2C_MAX_TIMEOUT);
@endverbatim
* ============================================================================
*/
CSL_Status I2C_write(Uint16 *i2cWrBuf,
Uint16 dataLength,
Uint16 slaveAddr,
Bool masterMode,
Uint16 startStopFlag,
Uint16 timeout)
{
Uint16 looper;
Uint16 dataCount;
Uint16 statusByte;
if((i2cWrBuf != NULL) && (dataLength !=0))
{
/* check for bus busy */
for(looper = 0; looper < timeout; looper++)
{
statusByte = CSL_FEXT(i2cHandle->i2cRegs->ICSTR, I2C_ICSTR_BB);
if(statusByte == FALSE)
{
break;
}
}
if(looper >= timeout)
{
/* bus busy timeout error */
return(CSL_I2C_BUS_BUSY_ERR);
}
/* Set the Tx mode */
CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_TRX, SET);
/* Set the data length */
CSL_FINS(i2cHandle->i2cRegs->ICCNT, I2C_ICCNT_ICDC, dataLength);
if(masterMode == TRUE)
{
/* Set the slave address */
CSL_FINS(i2cHandle->i2cRegs->ICSAR, I2C_ICSAR_SADDR, slaveAddr);
/* Enable Master mode */
CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_MST, SET);
/* Set the stop bit */
if((startStopFlag & CSL_I2C_STOP) == CSL_I2C_STOP)
{
CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_STP, SET);
}
/* Set the start bit */
if((startStopFlag & CSL_I2C_START) == CSL_I2C_START)
{
CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_STT, SET);
}
}
else
{
/* Disable Master mode */
CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_MST, CLEAR);
}
for(dataCount = 0; dataCount < dataLength; dataCount++)
{
/* Check for ICXRDY status */
for(looper = 0; looper < timeout; looper++)
{
statusByte = CSL_FEXT(i2cHandle->i2cRegs->ICSTR,
I2C_ICSTR_ICXRDY);
if(statusByte == TRUE)
{
break;
}
}
if(looper >= timeout)
{
return(CSL_I2C_TIMEOUT_ERROR);
}
/* Write data to the data Tx register */
CSL_FINS(i2cHandle->i2cRegs->ICDXR, I2C_ICDXR_D, *i2cWrBuf++);
for(looper = 0; looper < timeout; looper++)
{
/* Check for NACK status */
statusByte = CSL_FEXT(i2cHandle->i2cRegs->ICSTR,
I2C_ICSTR_NACK);
if(statusByte == FALSE)
{
break;
}
}
if(looper >= timeout)
{
return(CSL_I2C_NACK_ERR);
}
}
}
else
{
return(CSL_ESYS_INVPARAMS);
}
return(CSL_SOK);
}
/** ============================================================================
* @n@b I2C_read
*
* @b Description
* @n Receives the I2C data from the I2C device.
*
* @b Arguments
* @verbatim
i2cRdBuf I2C Data buffer pointer
dataLength Number bytes to receive
slaveAddr Address of the slave device
masterMode Master mode flag
startStopFlag Flag for the start and stop bits
timeout Time out variable
checkBus Check Bus busy flag
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Returned for success
* @li CSL_ESYS_INVPARAMS - Invalid parameter
* @li CSL_I2C_BUS_BUSY_ERR - Busy Bit Error
* @li CSL_I2C_TIMEOUT_ERROR - Time out Error has occured
* @li CSL_I2C_RECEIVE_OVERFLOW_ERR - Recieve Register over flow error
*
* <b> Pre Condition </b>
* @n I2C_init and I2C_config/I2C_setup should be called successfully
*
* <b> Post Condition </b>
* @n Receives the I2C data
*
* @b Modifies
* @n I2C data buffer
*
* @b Example
* @verbatim
#define CSL_I2C_SYS_CLK (12) // In MHz
#define CSL_I2C_BUS_FREQ (10) // In KHz
#define CSL_I2C_DATA_SIZE (16)
#define CSL_I2C_EEPROM_ADDR (0x50)
#define CSL_I2CEEPROM_ADDR_SIZE (2)
Uint16 i2cDataBuf[CSL_I2C_DATA_SIZE];
CSL_Status status;
CSL_I2cSetup i2cSetup;
i2cSetup.addrMode = CSL_I2C_ADDR_7BIT;
i2cSetup.bitCount = CSL_I2C_BC_8BITS;
i2cSetup.loopBack = CSL_I2C_LOOPBACK_DISABLE;
i2cSetup.freeMode = CSL_I2C_FREEMODE_DISABLE;
i2cSetup.repeatMode = CSL_I2C_REPEATMODE_DISABLE;
i2cSetup.ownAddr = CSL_I2C_OWN_ADDR;
i2cSetup.sysInputClk = CSL_I2C_SYS_CLK;
i2cSetup.i2cBusFreq = CSL_I2C_BUS_FREQ;
status = I2C_init(CSL_I2C0);
....
status = I2C_setup(&i2cSetup);
....
....
status = I2C_read(i2cDataBuf, CSL_I2C_DATA_SIZE, CSL_I2C_EEPROM_ADDR,
TRUE, 1, CSL_I2C_MAX_TIMEOUT, FALSE);
@endverbatim
* ============================================================================
*/
CSL_Status I2C_read(Uint16 *i2cRdBuf,
Uint16 dataLength,
Uint16 slaveAddr,
Bool masterMode,
Uint16 startStopFlag,
Uint16 timeout,
Bool checkBus)
{
Uint16 looper;
Uint16 dataCount;
Uint16 statusByte;
if((i2cRdBuf != NULL) && (dataLength !=0))
{
/* Set the Rx mode */
CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_TRX, CLEAR);
/* Set the data length */
CSL_FINS(i2cHandle->i2cRegs->ICCNT, I2C_ICCNT_ICDC, dataLength);
if(masterMode == TRUE)
{
/* Set the slave address */
CSL_FINS(i2cHandle->i2cRegs->ICSAR, I2C_ICSAR_SADDR, slaveAddr);
/* Enable Master mode */
CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_MST, SET);
/* Set the stop bit */
if((startStopFlag & CSL_I2C_STOP) == CSL_I2C_STOP)
{
CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_STP, SET);
}
/* Set the start bit */
if((startStopFlag & CSL_I2C_START) == CSL_I2C_START)
{
CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_STT, SET);
}
}
else
{
/* Disable Master mode */
CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_MST, CLEAR);
}
if(checkBus == TRUE)
{
/* check for bus busy */
for(looper = 0; looper < timeout; looper++)
{
statusByte = CSL_FEXT(i2cHandle->i2cRegs->ICSTR, I2C_ICSTR_BB);
if (statusByte == FALSE)
{
break;
}
}
if(looper >= timeout)
{
/* bus busy timeout error */
return(CSL_I2C_BUS_BUSY_ERR);
}
}
for(dataCount = 0; dataCount < dataLength; dataCount++)
{
/* Check for ICRRDY status */
for(looper = 0; looper < timeout; looper++)
{
statusByte = CSL_FEXT(i2cHandle->i2cRegs->ICSTR,
I2C_ICSTR_ICRRDY);
if(statusByte == TRUE)
{
break;
}
}
if(looper >= timeout)
{
return(CSL_I2C_TIMEOUT_ERROR);
}
/* Read data from the data Rx register */
*i2cRdBuf++ = CSL_FEXT(i2cHandle->i2cRegs->ICDRR, I2C_ICDRR_D);
/* Check for Overflow status */
statusByte = CSL_FEXT(i2cHandle->i2cRegs->ICSTR, I2C_ICSTR_RSFULL);
if(statusByte == TRUE)
{
return(CSL_I2C_RECEIVE_OVERFLOW_ERR);
}
}
}
else
{
return(CSL_ESYS_INVPARAMS);
}
return(CSL_SOK);
}