void CSP_TmrInit (void)
{
CSP_DEV_NBR per_nbr;
CSP_DEV_NBR tmr_nbr;
CSP_TMR_REG *p_tmr_reg;
CPU_SR_ALLOC();
for (tmr_nbr = CSP_TMR_NBR_00; tmr_nbr <= CSP_TMR_NBR_03; tmr_nbr++) {
p_tmr_reg = (CSP_TMR_REG *)CSP_TmrAddrTbl[tmr_nbr];
per_nbr = (CSP_DEV_NBR )CSP_TmrPerTbl[tmr_nbr];
CPU_CRITICAL_ENTER();
CSP_PM_PerClkEn(per_nbr);
p_tmr_reg->MCR = DEF_BIT_NONE;
p_tmr_reg->MRx[0] = 0u;
p_tmr_reg->MRx[1] = 0u;
p_tmr_reg->MRx[2] = 0u;
p_tmr_reg->IR = DEF_BIT_FIELD(5u, 0u);
p_tmr_reg->TCR = DEF_BIT_NONE;
p_tmr_reg->MCR = DEF_BIT_NONE;
p_tmr_reg->EMR = DEF_BIT_NONE;
CSP_PM_PerClkDis(per_nbr);
CPU_CRITICAL_EXIT();
}
}
static void SerialBSP_AT91_USART3_ClkEn (SERIAL_ERR *perr)
{
CSP_IntDis(CSP_INT_CTRL_NBR_MAIN, CSP_INT_SRC_NBR_UART_03);
CSP_PM_PerClkEn(CSP_PM_PER_CLK_NBR_UART_03);
*perr = SERIAL_ERR_NONE;
}
CPU_BOOLEAN CSP_DMA_InitExt (void)
{
CSP_DMA_REG *p_dma_reg;
CSP_DMA_CH_REG *p_dma_ch_reg;
CSP_DMA_CH *p_ch_tbl;
CPU_INT08U ch_nbr;
CSP_IntDis(CSP_INT_CTRL_NBR_MAIN, /* Disable DMA interrupts */
CSP_INT_SRC_NBR_DMA_00);
CSP_PM_PerClkEn(CSP_PM_PER_CLK_NBR_DMA_00); /* Enable DMA controller clock. */
p_dma_reg = (CSP_DMA_REG *)CSP_ADDR_DMA_REG;
p_dma_reg->IntTCClr = DEF_INT_08_MASK; /* Clear all pending interrupts. */
p_dma_reg->IntErrClr = DEF_INT_08_MASK;
/* Initialize DMA channels register & table */
for (ch_nbr = 0u; ch_nbr < CSP_DMA_CH_MAX_NBR; ch_nbr++) {
p_dma_ch_reg = &(p_dma_reg->CHx[ch_nbr]);
p_ch_tbl = &CSP_DMA_ChTbl[ch_nbr];
p_ch_tbl->State = CSP_DMA_CH_STATE_FREE;
p_ch_tbl->CallBackFnctPtr = (CSP_DMA_CALLBACK_PTR )0;
p_ch_tbl->CallBackArgPtr = (void *)0;
p_dma_ch_reg->SrcAddr = 0u;
p_dma_ch_reg->DestAddr = 0u;
p_dma_ch_reg->LLI = 0u;
p_dma_ch_reg->Ctrl = DEF_BIT_NONE;
p_dma_ch_reg->Cfg = DEF_BIT_NONE;
}
p_dma_reg->Cfg = CSP_DMA_REG_CFG_DMA_EN; /* Enable DMA controller. */
(void)CSP_IntVectReg((CSP_DEV_NBR )CSP_INT_CTRL_NBR_MAIN, /* Install global DMA interrupt handler. */
(CSP_DEV_NBR )CSP_INT_SRC_NBR_DMA_00,
(CPU_FNCT_PTR )CSP_DMA_IntHandler,
(void *)0);
CSP_IntEn(CSP_INT_CTRL_NBR_MAIN,
CSP_INT_SRC_NBR_DMA_00);
return (DEF_OK);
}
CPU_BOOLEAN CSP_TmrOutCmpCfg (CSP_DEV_NBR tmr_nbr,
CSP_DEV_NBR pin,
CSP_OPT pin_action,
CPU_INT32U freq)
{
CSP_TMR_REG *p_tmr_reg;
CPU_INT08U match_nbr;
CPU_INT32U match_val;
CPU_INT32U per_freq;
CSP_DEV_NBR per_nbr;
CPU_SR_ALLOC();
/* ---------------- ARGUMENTS CHECKING -------------- */
#if (CSP_CFG_ARG_CHK_EN == DEF_ENABLED)
if (tmr_nbr > CSP_TMR_NBR_01) {
return (DEF_FAIL);
}
if (pin > CSP_TMR_PIN_OUT_NBR_03) {
return (DEF_FAIL);
}
if (freq == 0u) {
return (DEF_FAIL);
}
#endif
p_tmr_reg = (CSP_TMR_REG *)CSP_TmrAddrTbl[tmr_nbr];
per_nbr = (CSP_DEV_NBR )CSP_TmrPerTbl[tmr_nbr];
match_nbr = pin,
per_freq = CSP_PM_PerClkFreqGet(per_nbr); /* Get the peripheral clock. */
if (freq > per_freq) {
return (DEF_FAIL);
}
match_val = ((2u * per_freq / freq) + 1u) / 2u;
if (match_val == 0u) {
return (DEF_FAIL);
}
CSP_PM_PerClkEn(per_nbr); /* Enable Peripherical clock. */
CPU_CRITICAL_ENTER();
DEF_BIT_CLR(p_tmr_reg->EMR, DEF_BIT_MASK(3u, (2u * match_nbr) + 4u));
switch (pin_action) {
case CSP_TMR_OPT_PIN_OUT_NONE:
break;
case CSP_TMR_OPT_PIN_OUT_CLR:
DEF_BIT_SET(p_tmr_reg->EMR, DEF_BIT_MASK(1u, (2u * match_nbr) + 4u));
break;
case CSP_TMR_OPT_PIN_OUT_SET:
DEF_BIT_SET(p_tmr_reg->EMR, DEF_BIT_MASK(2u, (2u * match_nbr) + 4u));
break;
case CSP_TMR_OPT_PIN_OUT_TOGGLE:
DEF_BIT_SET(p_tmr_reg->EMR, DEF_BIT_MASK(3u, (2u * match_nbr) + 4u));
break;
default:
CPU_CRITICAL_EXIT();
return (DEF_FAIL);
}
/* Disable the Interrupt, Reset and Stop features on */
/* ... Match channel 0, 1, 2 or 3. */
DEF_BIT_CLR(p_tmr_reg->MCR, CSP_TMR_MASK_MCR_MRx(match_nbr));
DEF_BIT_CLR(p_tmr_reg->TCR, CSP_TMR_MASK_TCR_MODE); /* Clear the Mode */
DEF_BIT_SET(p_tmr_reg->TCR, CSP_TMR_BIT_TCR_TMR_MODE); /* Set the Timer Mode */
p_tmr_reg->PR = 0u; /* Set the prescaler to 0 */
p_tmr_reg->MRx[match_nbr] = match_val;
p_tmr_reg->TCR = CSP_TMR_BIT_CR_RST; /* Reset the timer */
/* Enable Interrupt and Reset when TC matches MR0, ... */
/* MR1, MR2, etc */
DEF_BIT_SET(p_tmr_reg->MCR, CSP_TMR_BIT_MCR_MRIx(match_nbr) |
CSP_TMR_BIT_MCR_MRRx(match_nbr));
CPU_CRITICAL_EXIT();
return (DEF_OK);
}
CPU_BOOLEAN CSP_TmrCfg (CSP_DEV_NBR tmr_nbr,
CPU_INT32U freq)
{
CSP_TMR_REG *p_tmr_reg;
CPU_INT32U match_val;
CPU_INT32U per_freq;
CSP_DEV_NBR per_nbr;
CPU_SR_ALLOC();
#if (CSP_CFG_ARG_CHK_EN == DEF_ENABLED)
if (tmr_nbr > CSP_TMR_NBR_03) {
return (DEF_FAIL);
}
#endif
p_tmr_reg = (CSP_TMR_REG *)CSP_TmrAddrTbl[tmr_nbr];
per_nbr = (CSP_DEV_NBR )CSP_TmrPerTbl[tmr_nbr];
if (freq == 0u) { /* -------- FREE RUNNING TIMER CONFIGURATION --------- */
CSP_PM_PerClkEn(per_nbr); /* Enable peripheral clock */
CPU_CRITICAL_ENTER();
p_tmr_reg->MCR = DEF_BIT_NONE; /* Disable theInterrupt, Reset and Stop feauture on */
/* ... Match channels. */
DEF_BIT_CLR(p_tmr_reg->TCR, CSP_TMR_MASK_TCR_MODE); /* Clear the Mode. */
DEF_BIT_SET(p_tmr_reg->TCR, CSP_TMR_BIT_TCR_TMR_MODE); /* Set the Timer Mode. */
p_tmr_reg->PR = 0u; /* Set the prescaler to 0. */
p_tmr_reg->TCR = CSP_TMR_BIT_CR_RST; /* Reset the timer. */
CPU_CRITICAL_EXIT();
} else { /* ---------- PERIODIC TIMER CONFIGURATION ----------- */
per_freq = CSP_PM_PerClkFreqGet(per_nbr); /* Get the peripheral clock. */
if (freq > per_freq) {
return (DEF_FAIL);
}
match_val = ((2u * per_freq / freq) + 1u) / 2u;
if (match_val == 0u) {
return (DEF_FAIL);
}
CSP_PM_PerClkEn(per_nbr); /* Enable peripheral clock. */
CPU_CRITICAL_ENTER();
DEF_BIT_CLR(p_tmr_reg->EMR, DEF_BIT_MASK(3u, (2u * 0u) + 4u));
CPU_CRITICAL_EXIT();
/* Disable the Interrupt, Reset and Stop features on */
/* ... Match channel 0, 1, 2 or 3. */
DEF_BIT_CLR(p_tmr_reg->MCR, CSP_TMR_MASK_MCR_MRx(0u));
DEF_BIT_CLR(p_tmr_reg->TCR, CSP_TMR_MASK_TCR_MODE); /* Clear the Mode */
DEF_BIT_SET(p_tmr_reg->TCR, CSP_TMR_BIT_TCR_TMR_MODE); /* Set the Timer Mode */
p_tmr_reg->PR = 0u; /* Set the prescaler to 0 */
p_tmr_reg->MRx[0] = match_val;
p_tmr_reg->TCR = CSP_TMR_BIT_CR_RST; /* Reset the timer */
/* Enable Interrupt and Reset when TC matches MR0, ... */
/* MR1, MR2, etc */
DEF_BIT_SET(p_tmr_reg->MCR, CSP_TMR_BIT_MCR_MRIx(0u) |
CSP_TMR_BIT_MCR_MRRx(0u));
CPU_CRITICAL_EXIT();
}
return (DEF_OK);
}
static void SerialBSP_AT91_USART3_ClkDis (SERIAL_ERR *perr)
{
CSP_PM_PerClkEn(CSP_PM_PER_CLK_NBR_UART_03);
*perr = SERIAL_ERR_NONE;
}