/*
* Early initialization of comm channels. Must not rely
* on interrupts, yet. Interrupt operation can be enabled
* in _bsp_board_init().
*/
void
cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
static int init = 0; // It's wrong to do this more than once
int chan = 0;
if (init) return;
init++;
// Setup procs in the vector table
#if CYGNUM_HAL_QUICC_SMC1 > 0
// Set up SMC1
cyg_hal_smcx_init_channel(&ports[chan], QUICC_CPM_SMC1);
CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable!
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sxx_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sxx_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_smcx_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_sxx_getc_timeout);
chan++;
#endif
#if CYGNUM_HAL_QUICC_SMC2 > 0
// Set up SMC2
cyg_hal_smcx_init_channel(&ports[chan], QUICC_CPM_SMC2);
CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable!
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sxx_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sxx_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_smcx_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_sxx_getc_timeout);
chan++;
#endif
#if CYGNUM_HAL_QUICC_SCC1 > 0
// Set up SCC1
cyg_hal_sccx_init_channel(&ports[chan], QUICC_CPM_SCC1);
CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable!
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sxx_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sxx_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_sccx_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_sxx_getc_timeout);
chan++;
#endif
#if CYGNUM_HAL_QUICC_SCC2 > 0
// Set up SCC2
cyg_hal_sccx_init_channel(&ports[chan], QUICC_CPM_SCC2);
CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable!
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sxx_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sxx_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_sccx_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_sxx_getc_timeout);
chan++;
#endif
#if CYGNUM_HAL_QUICC_SCC3 > 0
// Set up SCC3
cyg_hal_sccx_init_channel(&ports[chan], QUICC_CPM_SCC3);
CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable!
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sxx_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sxx_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_sccx_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_sxx_getc_timeout);
chan++;
#endif
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
static void cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
// Disable interrupts.
HAL_INTERRUPT_MASK(channels[0].isr_vector);
HAL_INTERRUPT_MASK(channels[1].isr_vector);
#ifdef CONFIG_MT7628_ASIC
HAL_INTERRUPT_MASK(channels[2].isr_vector);
#endif
// Init channels
cyg_hal_plf_serial_init_channel((void*)&channels[0]);
cyg_hal_plf_serial_init_channel((void*)&channels[1]);
#ifdef CONFIG_MT7628_ASIC
cyg_hal_plf_serial_init_channel((void*)&channels[2]);
#endif
// Setup procs in the vector table
// Set channel 0
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[0]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
// Set channel 1
CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[1]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
#ifdef CONFIG_MT7628_ASIC
// Set channel 2
CYGACC_CALL_IF_SET_CONSOLE_COMM(2);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[2]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
#endif
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
