/*****************************************************
**FUNCTION :: ChipSetField_0367ter
**ACTION :: Set value of a field in the chip
**PARAMS IN :: hChip ==> Handle to the chip
** FieldId ==> Id of the field
** Value ==> Value to write
**PARAMS OUT:: NONE
**RETURN :: Error
*****************************************************/
YW_ErrorType_T ChipSetField_0367qam(TUNER_IOREG_DeviceMap_t *DeviceMap, IOARCH_Handle_t IOHandle,U32 FieldId,int Value)
{
int regValue;
int mask;
int Sign;
int Bits;
int Pos;
if(DeviceMap)
{
//if(!DeviceMap->Error)
{
if (FieldId <= 0xffff)
{
ChipSetOneRegister_0367qam(DeviceMap, IOHandle, FieldId, Value);
}
else
{
regValue=ChipGetOneRegister_0367qam(DeviceMap, IOHandle,(FieldId >> 16)&0xFFFF); /* Read the register */
Sign = ChipGetFieldSign(FieldId);
mask = ChipGetFieldMask(FieldId);
Pos = ChipGetFieldPosition(mask);
Bits = ChipGetFieldBits(mask,Pos);
if(Sign == CHIP_SIGNED)
Value = (Value > 0 ) ? Value : Value + (Bits); /* compute signed fieldval */
Value = mask & (Value << Pos); /* Shift and mask value */
regValue=(regValue & (~mask)) + Value; /* Concat register value and fieldval */
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,(FieldId >> 16)&0xFFFF,regValue); /* Write the register */
}
}
//else
//DeviceMap->Error = YWHAL_ERROR_BAD_PARAMETER;
}
else
return YWHAL_ERROR_INVALID_HANDLE;
/*****************************************************
--FUNCTION :: FE_367qam_Algo
--ACTION :: Driver functio of the STV0367QAM chip
--PARAMS IN :: *pIntParams ==> Demod handle
-- Tuner handle
Search frequency
Symbolrate
QAM Size
DerotOffset
SweepRate
Search Range
Master clock
ADC clock
Structure for result storage
--PARAMS OUT:: NONE
--RETURN :: Handle to STV0367QAM
--***************************************************/
static FE_367qam_SIGNALTYPE_t
D0367qam_Algo(TUNER_IOREG_DeviceMap_t *DemodDeviceMap,
IOARCH_Handle_t DemodIOHandle,
FE_367qam_InternalParams_t *pIntParams)
{
FE_367qam_SIGNALTYPE_t signalType=FE_367qam_NOAGC; /* Signal search statusinitialization */
U32 QAMFEC_Lock, QAM_Lock, u32_tmp ;
BOOL TunerLock = FALSE;
U32 LockTime, TRLTimeOut, AGCTimeOut, CRLSymbols, CRLTimeOut, EQLTimeOut, DemodTimeOut, FECTimeOut;
U8 TrackAGCAccum;
TUNER_IOREG_DeviceMap_t *DeviceMap = DemodDeviceMap;
IOARCH_Handle_t IOHandle = DemodIOHandle;
U32 FreqResult = 0;
/* Timeouts calculation */
/* A max lock time of 25 ms is allowed for delayed AGC */
AGCTimeOut = 25;
/* 100000 symbols needed by the TRL as a maximum value */
TRLTimeOut = 100000000/pIntParams->SymbolRate_Bds;
/* CRLSymbols is the needed number of symbols to achieve a lock within [-4%,+4%] of the symbol rate.
CRL timeout is calculated for a lock within [-SearchRange_Hz, +SearchRange_Hz].
EQL timeout can be changed depending on the micro-reflections we want tohandle.
A characterization must be performed with these echoes to get new timeoutvalues.
*/
switch (pIntParams->Modulation)
{
case FE_CAB_MOD_QAM16:
CRLSymbols = 150000;
EQLTimeOut = 100;
break;
case FE_CAB_MOD_QAM32:
CRLSymbols = 250000;
EQLTimeOut = 100;
break;
case FE_CAB_MOD_QAM64:
CRLSymbols = 200000;
EQLTimeOut = 100;
break;
case FE_CAB_MOD_QAM128:
CRLSymbols = 250000;
EQLTimeOut = 100;
break;
case FE_CAB_MOD_QAM256:
CRLSymbols = 250000;
EQLTimeOut = 100;
break;
default:
CRLSymbols = 200000;
EQLTimeOut = 100;
break;
}
if (pIntParams->SearchRange_Hz < 0)
{
CRLTimeOut = (25*CRLSymbols*(-pIntParams->SearchRange_Hz/1000))/(pIntParams->SymbolRate_Bds/1000);
}
else
{
CRLTimeOut = (25*CRLSymbols*(pIntParams->SearchRange_Hz/1000))/(pIntParams->SymbolRate_Bds/1000);
}
CRLTimeOut = (1000*CRLTimeOut)/pIntParams->SymbolRate_Bds;
/* Timeouts below 50ms are coerced */
if (CRLTimeOut <50) CRLTimeOut = 50;
/* A maximum of 100 TS packets is needed to get FEC lock even in case thespectrum inversion needs to be changed.
This is equal to 20 ms in case of the lowest symbol rate of 0.87Msps
*/
FECTimeOut = 20;
DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut;
/* Reset the TRL to ensure nothing starts until the
AGC is stable which ensures a better lock time
*/
ChipSetOneRegister_0367qam(DeviceMap,IOHandle,R367qam_CTRL_1,0x04);
/* Set AGC accumulation time to minimum and lock threshold to maximum inorder to speed up the AGC lock */
TrackAGCAccum = ChipGetField_0367qam(DeviceMap,IOHandle,F367qam_AGC_ACCUMRSTSEL);
ChipSetField_0367qam(DeviceMap,IOHandle,F367qam_AGC_ACCUMRSTSEL,0x0);
/* Modulus Mapper is disabled */
ChipSetField_0367qam(DeviceMap,IOHandle,F367qam_MODULUSMAP_EN,0);
/* Disable the sweep function */
ChipSetField_0367qam(DeviceMap,IOHandle,F367qam_SWEEP_EN,0);
/* The sweep function is never used, Sweep rate must be set to 0 */
/* Set the derotator frequency in Hz */
//FE_367qam_SetDerotFreq(DeviceMap,IOHandle,pIntParams->AdcClock_Hz,(1000*(S32)FE_TunerGetIF_Freq(pIntParams->hTuner)+pIntParams->DerotOffset_Hz));
FE_367qam_SetDerotFreq(DeviceMap,IOHandle,pIntParams->AdcClock_Hz,(1000*(36125000/1000)+pIntParams->DerotOffset_Hz)); //question if freq
/* Disable the Allpass Filter when the symbol rate is out of range */
if((pIntParams->SymbolRate_Bds > 10800000)||(pIntParams->SymbolRate_Bds <1800000))
{
ChipSetField_0367qam(DeviceMap,IOHandle,F367qam_ADJ_EN,0);
ChipSetField_0367qam(DeviceMap,IOHandle,F367qam_ALLPASSFILT_EN,0);
}
#if 0
/* Check if the tuner is locked */
if (Inst->DriverParam.Cab.TunerDriver.tuner_IsLocked != NULL)
{
Inst->DriverParam.Cab.TunerDriver.tuner_IsLocked(Handle, &TunerLock);
}
#else
D0367qam_TunerIsLock(DeviceMap, &TunerLock);
#endif /* 0 */
if (TunerLock == 0)
{
return FE_367qam_NOTUNER;
}
/* Relase the TRL to start demodulator acquisition */
/* Wait for QAM lock */
LockTime=0;
ChipSetOneRegister_0367qam(DeviceMap,IOHandle,R367qam_CTRL_1,0x00);
do
{
QAM_Lock = ChipGetField_0367qam(DeviceMap,IOHandle,F367qam_FSM_STATUS);
if ((LockTime >= (DemodTimeOut - EQLTimeOut)) && (QAM_Lock == 0x04))
/* We don't wait longer, the frequency/phase offset must be too big */
LockTime = DemodTimeOut;
else if ((LockTime >= (AGCTimeOut + TRLTimeOut))&&(QAM_Lock == 0x02))
/* We don't wait longer, either there is no signal or it is not the rightsymbol rate or it is an analog carrier */
{
LockTime = DemodTimeOut;
ChipGetRegisters_0367qam(DeviceMap,IOHandle,R367qam_AGC_PWR_RD_L,3);
u32_tmp = ChipGetFieldImage_0367qam(DeviceMap,IOHandle,F367qam_AGC_PWR_WORD_LO)
+(ChipGetFieldImage_0367qam(DeviceMap,IOHandle,F367qam_AGC_PWR_WORD_ME)<<8)
+(ChipGetFieldImage_0367qam(DeviceMap,IOHandle,F367qam_AGC_PWR_WORD_HI)<<16);
if (u32_tmp>=131072)
u32_tmp = 262144 - u32_tmp;
u32_tmp=u32_tmp/(PowOf2(11-ChipGetField_0367qam(DeviceMap,IOHandle,F367qam_AGC_IF_BWSEL)));
if(u32_tmp<ChipGetField_0367qam(DeviceMap,IOHandle,F367qam_AGC_PWRREF_LO)+256*ChipGetField_0367qam(DeviceMap,IOHandle,F367qam_AGC_PWRREF_HI) - 10)
QAM_Lock = 0x0f;
}
else
{
ChipWaitOrAbort_0367qam(FALSE, 10); /* wait 10 ms */
LockTime +=10;
}
}
while(((QAM_Lock != 0x0c)&&(QAM_Lock != 0x0b)) && (LockTime<DemodTimeOut));
if ((QAM_Lock == 0x0c)||(QAM_Lock == 0x0b))
{
/* Wait for FEC lock */
LockTime = 0;
do
{
ChipWaitOrAbort_0367qam(FALSE, 5);/* wait 5 ms */
LockTime +=5;
QAMFEC_Lock = ChipGetField_0367qam(DeviceMap,IOHandle,F367qam_QAMFEC_LOCK);
}
while(!QAMFEC_Lock && (LockTime<FECTimeOut));
}
else
QAMFEC_Lock = 0;
if(QAMFEC_Lock)
{
signalType = FE_367qam_DATAOK;
pIntParams->DemodResult.Modulation = pIntParams->Modulation;
pIntParams->DemodResult.SpectInv = ChipGetField_0367qam(DeviceMap,IOHandle,F367qam_QUAD_INV);
#if 0
//lwj add begin
if (Inst->DriverParam.Cab.TunerDriver.tuner_GetFreq != NULL) //lwj add
{
Inst->DriverParam.Cab.TunerDriver.tuner_GetFreq(Handle, &FreqResult);
}
#else
FreqResult = D0367qam_GeFrequencyKhz(DeviceMap, IOHandle);
#endif /* 0 */
//lwj add end
//if (FE_TunerGetIF_Freq(pIntParams->hTuner) != 0)
#if 0 //lwj remove
if (0) //IF 为０
{
if(FE_TunerGetIF_Freq(pIntParams->hTuner)>pIntParams->AdcClock_Hz/1000)
{
pIntParams->DemodResult.Frequency_kHz = FreqResult -FE_367qam_GetDerotFreq(DeviceMap,IOHandle,pIntParams->AdcClock_Hz)- pIntParams->AdcClock_Hz/1000 + FE_TunerGetIF_Freq(pIntParams->hTuner);
}
else
{
pIntParams->DemodResult.Frequency_kHz = FreqResult -FE_367qam_GetDerotFreq(DeviceMap,IOHandle,pIntParams->AdcClock_Hz)+FE_TunerGetIF_Freq(pIntParams->hTuner);
}
}
else
#endif
{
pIntParams->DemodResult.Frequency_kHz = FreqResult + FE_367qam_GetDerotFreq(DeviceMap,IOHandle,pIntParams->AdcClock_Hz) - pIntParams->AdcClock_Hz/4000;
}
pIntParams->DemodResult.SymbolRate_Bds = FE_367qam_GetSymbolRate(DeviceMap,IOHandle,pIntParams->MasterClock_Hz);
pIntParams->DemodResult.Locked = 1;
/* ChipSetField(pIntParams->hDemod,F367qam_AGC_ACCUMRSTSEL,7);*/
}
else
{
switch(QAM_Lock)
{
case 1:
signalType = FE_367qam_NOAGC;
break;
case 2:
signalType = FE_367qam_NOTIMING;
break;
case 3:
signalType = FE_367qam_TIMINGOK;
break;
case 4:
signalType = FE_367qam_NOCARRIER;
break;
case 5:
signalType = FE_367qam_CARRIEROK;
break;
case 7:
signalType = FE_367qam_NOBLIND;
break;
case 8:
signalType = FE_367qam_BLINDOK;
break;
case 10:
signalType = FE_367qam_NODEMOD;
break;
case 11:
signalType = FE_367qam_DEMODOK;
break;
case 12:
signalType = FE_367qam_DEMODOK;
break;
case 13:
signalType = FE_367qam_NODEMOD;
break;
case 14:
signalType = FE_367qam_NOBLIND;
break;
case 15:
signalType = FE_367qam_NOSIGNAL;
break;
default:
break;
}
}
/* Set the AGC control values to tracking values */
ChipSetField_0367qam(DeviceMap,IOHandle,F367qam_AGC_ACCUMRSTSEL,TrackAGCAccum);
return signalType;
}
YW_ErrorType_T D0367qam_Init(TUNER_IOREG_DeviceMap_t *DeviceMap,
IOARCH_Handle_t IOHandle,
TUNER_TunerType_T TunerType)
{
U16 i, j = 1;
for (i = 1; i<= DeviceMap->Registers;i++)
{
ChipUpdateDefaultValues_0367qam(DeviceMap, IOHandle, Def367qamVal[i-1].Addr, Def367qamVal[i-1].Value, i-1);
if (i != STV0367qam_NBREGS)
{
if(Def367qamVal[i].Addr==Def367qamVal[i-1].Addr + 1)
{
j++;
}
else if (j == 1)
{
ChipSetOneRegister_0367qam(DeviceMap, IOHandle, Def367qamVal[i-1].Addr, Def367qamVal[i-1].Value);
}
else
{
ChipSetRegisters_0367qam(DeviceMap, IOHandle, Def367qamVal[i-j].Addr, j);
j = 1;
}
}
else
{
if (j == 1)
{
ChipSetOneRegister_0367qam(DeviceMap, IOHandle, Def367qamVal[i-1].Addr, Def367qamVal[i-1].Value);
}
else
{
ChipSetRegisters_0367qam(DeviceMap, IOHandle, Def367qamVal[i-j].Addr, j);
j = 1;
}
}
}
ChipSetField_0367qam(DeviceMap, IOHandle, F367qam_BERT_ON, 0); /* restart a new BER count */
ChipSetField_0367qam(DeviceMap, IOHandle, F367qam_BERT_ON, 1); /* restart a new BER count */
ChipSetField_0367qam(DeviceMap, IOHandle,F367qam_OUTFORMAT,0x00);//FE_TS_PARALLEL_PUNCT_CLOCK
ChipSetField_0367qam(DeviceMap, IOHandle,F367qam_CLK_POLARITY, 0x01); //FE_TS_RISINGEDGE_CLOCK
ChipSetField_0367qam(DeviceMap, IOHandle,F367qam_SYNC_STRIP,0X00);//STFRONTEND_TS_SYNCBYTE_ON
ChipSetField_0367qam(DeviceMap, IOHandle,F367qam_CT_NBST,0x00);//STFRONTEND_TS_PARITYBYTES_OFF
ChipSetField_0367qam(DeviceMap, IOHandle,F367qam_TS_SWAP,0x00);//STFRONTEND_TS_SWAP_OFF
ChipSetField_0367qam(DeviceMap, IOHandle,F367qam_FIFO_BYPASS,0x01);//FE_TS_SMOOTHER_DEFAULT, ?? question
/* Here we make the necessary changes to the demod's registers depending on the tuner */
if(DeviceMap != NULL)
{
/*----------------------------------------------------------------------------------------*/
switch(TunerType) //important
{
case TUNER_TUNER_SHARP5469C:
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_ANACTRL,0x0D); /* PLL bypassed and disabled */
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_PLLMDIV,0x01); /* IC runs at 54MHz with a 27MHz crystal */
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_PLLNDIV,0x08);
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_PLLSETUP,0x18); /* ADC clock is equal to system clock */
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_ANACTRL,0x00); /* PLL enabled and used */
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_ANADIGCTRL,0x0b); /* Buffer Q disabled */
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_DUAL_AD12,0x04); /* ADCQ disabled */
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_FSM_SNR2_HTH,0x23); /* Improves the C/N lock limit */
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_IQ_QAM,0x01); /* ZIF/IF Automatic mode */
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_I2CRPT,0x22); /* I2C repeater configuration, value changes with I2C master clock */
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_EQU_FFE_LEAKAGE,0x63);
ChipSetOneRegister_0367qam(DeviceMap, IOHandle,R367qam_IQDEM_ADJ_EN,0x04); //lwj change 0x05 to 0x04
break;
default:
break;
}
}
return YW_NO_ERROR;
}
