// =========================================================================
// 函数功能: 由arm调用，唤醒dsp并使之处于复位态。
// 函数参数: start_address，dsp的入口地址
// 返回值 : 无
// =========================================================================
void Dcore_WakeupDspReset(void)
{
g_ptSysconfig0Reg->KICKR[0] = KICK0R_UNLOCK;
g_ptSysconfig0Reg->KICKR[1] = KICK1R_UNLOCK;
g_ptLpsc0Reg->MDCTL[cn_PSC0_DSP] &= ~(u32)LRST;
g_ptSysconfig0Reg->KICKR[0] = KICK0R_LOCK;
g_ptSysconfig0Reg->KICKR[1] = KICK1R_LOCK;
Cpucfg_EnableLPSC(cn_PSC0_DSP);
g_ptSysconfig0Reg->KICKR[0] = KICK0R_UNLOCK;
g_ptSysconfig0Reg->KICKR[1] = KICK1R_UNLOCK;
g_ptLpsc0Reg->MDCTL[cn_PSC0_DSP] |= LRST;
g_ptSysconfig0Reg->KICKR[0] = KICK0R_LOCK;
g_ptSysconfig0Reg->KICKR[1] = KICK1R_LOCK;
}
// =========================================================================
// 函数功能: 由arm调用，唤醒dsp并使之从start_address地址开始运行。调用本函数前，
// 必须先把代码加载到start_address所在的地址，dsp不可调用本函数。
// 函数参数: start_address，dsp的入口地址
// 返回值 : 无
// =========================================================================
void Dcore_WakeupDspRun(void (*start_address)(void))
{
g_ptSysconfig0Reg->KICKR[0] = KICK0R_UNLOCK;
g_ptSysconfig0Reg->KICKR[1] = KICK1R_UNLOCK;
g_ptLpsc0Reg->MDCTL[cn_PSC0_DSP] &= ~(u32)LRST;
g_ptSysconfig0Reg->HOST1CFG = (u32)start_address;
g_ptSysconfig0Reg->KICKR[0] = KICK0R_LOCK;
g_ptSysconfig0Reg->KICKR[1] = KICK1R_LOCK;
Cpucfg_EnableLPSC(cn_PSC0_DSP);
g_ptSysconfig0Reg->KICKR[0] = KICK0R_UNLOCK;
g_ptSysconfig0Reg->KICKR[1] = KICK1R_UNLOCK;
g_ptLpsc0Reg->MDCTL[cn_PSC0_DSP] |= LRST;
g_ptSysconfig0Reg->KICKR[0] = KICK0R_LOCK;
g_ptSysconfig0Reg->KICKR[1] = KICK1R_LOCK;
}
// =========================================================================
// 函数功能：spi口初始化,本驱动中，cs由spi模块按gpio的output方式访问，故cs一律设
// 置为gpio输出功能。根据l138的引脚管理特点，pinmux中的设置优先于
// spi模块中的设置，如果在pinmux中把spi0的scs0引脚设置为GP2[14]的
// 话，该引脚将由系统gpio模块控制，spi模块对它的所有设置和操作均无
// 效。因此，配置spi之前，应该先在pinmux中把该引脚配置为spi的cs功
// 能，ti的文档有误，pinmux中只能把这些引脚分配给spi使用，而不能指
// 定其为cs还是gpio。是否作为cs使用，由spi模块决定
// 输入参数：tpSpi，被操作的spi控制结构的地址
// tagpInConfig，配置结构，包含配置信息
// 输出参数：无
// 返回值 ：true=成功，false=失败
// =========================================================================
bool_t Spi_Init(volatile tagSpiReg * tpSpi, tagSpiConfig* tagpInConfig)
{
u32 u32Prescaler;
if(tpSpi == g_ptSpi0Reg)
Cpucfg_EnableLPSC(cn_PSC0_SPI0);
else if(tpSpi == g_ptSpi1Reg)
Cpucfg_EnableLPSC(cn_PSC1_SPI1);
else
return false;
if (tagpInConfig != NULL)
{
// reset tpSpi port.
tpSpi->GCR0 = 0;
tpSpi->GCR0 |= CN_SPI_RESET;
// config master/slave mode.
if (SPI_MODE_MASTER == tagpInConfig->tagMode)
{
// set clkmod and master for master mode.
tpSpi->GCR1 = CN_SPI_CLKMOD | CN_SPI_MASTER;
}
else if (SPI_MODE_SLAVE == tagpInConfig->tagMode)
{
// clear spigcr1 for slave mode.
tpSpi->GCR1 = 0;
}
else
{
goto error_exit;
}
// config pin options.
switch (tagpInConfig->tagPinOption)
{
case SPI_3PIN:
// enable tpSpi SOMI, SIMO, and CLK.
tpSpi->PC0 = SOMI | SIMO | CLK;
break;
case SPI_4PIN_CS:
// enable tpSpi SOMI, SIMO, CLK, and set cs[0~7] as gpio.
tpSpi->PC0 = SOMI | SIMO | CLK;
tpSpi->PC0 &= ~all_cs; //所有片选脚设为gpio
tpSpi->PC4 = all_cs; //拉高所有片选
tpSpi->PC1 |= all_cs; //所有片选脚设为输出
break;
case SPI_4PIN_EN:
// enable tpSpi SOMI, SIMO, CLK, and ENA.
tpSpi->PC0 = SOMI | SIMO | CLK | ENA;
break;
case SPI_5PIN:
// enable tpSpi SOMI, SIMO, CLK, SCS0, ENA and set cs[0~7] as gpio.
tpSpi->PC0 = SOMI | SIMO | CLK | ENA;
tpSpi->PC0 &= ~all_cs; //所有片选脚设为gpio
tpSpi->PC4 = all_cs; //拉高所有片选
tpSpi->PC1 |= all_cs; //所有片选脚设为输出
break;
default:
goto error_exit;
}
// config tpSpi direction, polarity, and phase.
tpSpi->FMT0 = 0;
if (SPI_SHIFT_LSB == tagpInConfig->tagShiftDir)
{
tpSpi->FMT0 |= SHIFTDIR;
}
if (tagpInConfig->polarity)
{
tpSpi->FMT0 |= POLARITY;
}
if (tagpInConfig->phase)
{
tpSpi->FMT0 |= PHASE;
}
// set the u32Prescaler and character length.
u32Prescaler = (((CN_CFG_PLL0_SYSCLK2 / tagpInConfig->freq) - 1) & 0xFF);
//u32Prescaler = 0x80;
tpSpi->FMT0 |= u32Prescaler << SHIFT_PRESCALE;
tpSpi->FMT0 |= (tagpInConfig->char_len&0x1f)<< SHIFT_CHARLEN;
tpSpi->DELAY = (8 << 24) | (8 << 16);
// disable interrupts.
tpSpi->INT = 0x00;
tpSpi->LVL = 0x00;
// enable tpSpi.
tpSpi->GCR1 |= CN_SPI_ENABLE;
}
return true;
error_exit:
if(tpSpi == g_ptSpi0Reg)
Cpucfg_DisableLPSC(cn_PSC0_SPI0);
else if(tpSpi == g_ptSpi1Reg)
Cpucfg_DisableLPSC(cn_PSC1_SPI1);
return false;
}
void Lcd_Display_On(void)
{
Cpucfg_EnableLPSC(cn_PSC1_LCDC);
}
void __lcd_hard_init(void)
{
u32 x,y,reg;
u16 *pdata;
// enable power and setup lcdc.
Cpucfg_EnableLPSC(cn_PSC1_LCDC);
/* Palette */
pdata = (u16*)(u8g_dsp_buffer - CN_PALETTE_SIZE);
#if CN_LCD_TYPE == CN_MODE_GREY_MONO
*pdata++ = 0;
*pdata++ = 15;
#elif CN_LCD_TYPE == CN_MODE_GREY_04
*pdata++ = 0;
*pdata++ = 5;
*pdata++ = 10;
*pdata++ = 15;
#elif CN_LCD_TYPE == CN_MODE_GREY_16
*pdata++ = 0;
*pdata++ = 1;
*pdata++ = 2;
*pdata++ = 3;
*pdata++ = 4;
*pdata++ = 5;
*pdata++ = 6;
*pdata++ = 7;
*pdata++ = 8;
*pdata++ = 9;
*pdata++ = 10;
*pdata++ = 11;
*pdata++ = 12;
*pdata++ = 13;
*pdata++ = 14;
*pdata++ = 15;
#endif
#if ((CN_LCD_TYPE == CN_MODE_GREY_MONO) || (CN_LCD_TYPE == CN_MODE_GREY_04) || (CN_LCD_TYPE == CN_MODE_GREY_16))
//以下分配LCD控制器所需的引脚
GPIO_CfgPinFunc(7,8,cn_p7_8_lcd_d0);
GPIO_CfgPinFunc(7,9,cn_p7_9_lcd_d1);
GPIO_CfgPinFunc(7,10,cn_p7_10_lcd_d2);
GPIO_CfgPinFunc(7,11,cn_p7_11_lcd_d3);
GPIO_CfgPinFunc(8,10,cn_p8_10_lcd_mclk);
GPIO_CfgPinFunc(8,11,cn_p8_11_lcd_pclk);
GPIO_CfgPinFunc(6,0,cn_p6_0_nlcd_ac_enb_cs);
GPIO_CfgPinFunc(8,8,cn_p8_8_lcd_vsync);
GPIO_CfgPinFunc(8,9,cn_p8_9_lcd_hsync);
g_ptSysconfig0Reg->MSTPRI[2] &= 0x0fffffff; //设置LCD数据传送次高优先级
g_ptSysconfig0Reg->MSTPRI[2] |= 0x10000000; //设置LCD数据传送次高优先级
// Turn raster controller off
g_ptLcdcReg->RASTER_CTRL &= 0xfffffffe;
// Clear status bits
g_ptLcdcReg->LCD_STAT = 0x000003ff;
// PCLK = 1.27MHz, 帧频66，raster mode
reg = CN_LCD_CLKVAL /(CN_LCD_SIZE_X * CN_LCD_SIZE_Y * 66) * 4;
g_ptLcdcReg->LCD_CTRL &= ~CN_LCDC_LCD_CTRL_CLKDIV_MASK;
g_ptLcdcReg->LCD_CTRL |= reg << CN_LCDC_LCD_CTRL_CLKDIV_SHIFT;
g_ptLcdcReg->LCD_CTRL |= CN_LCDC_LCD_CTRL_MODESEL_MASK;
g_ptLcdcReg->RASTER_CTRL =
(CN_LCDC_RASTER_CTRL_NIB_MODE_ENABLE << CN_LCDC_RASTER_CTRL_NIB_MODE_SHIFT)
+(CN_LCDC_RASTER_CTRL_MONO_COLOR_MONOCHROME << CN_LCDC_RASTER_CTRL_MONO_COLOR_SHIFT);
// HBP = 0; HFP = 0; HSW = 0x3; PPL = 0x13
g_ptLcdcReg->RASTER_TIMING_0 =
(4 << CN_LCDC_RASTER_TIMING_0_HBP_SHIFT)
+(4 << CN_LCDC_RASTER_TIMING_0_HFP_SHIFT)
+(4 << CN_LCDC_RASTER_TIMING_0_HSW_SHIFT)
+((CN_LCD_SIZE_X/16 -1)<< CN_LCDC_RASTER_TIMING_0_PPL_SHIFT);
// VBP = 0x3; VFP = 0x2; VSW = 0xA: LPP = 0xef;
g_ptLcdcReg->RASTER_TIMING_1 =
(10 << CN_LCDC_RASTER_TIMING_1_VBP_SHIFT)
+(9 << CN_LCDC_RASTER_TIMING_1_VFP_SHIFT)
+(5 << CN_LCDC_RASTER_TIMING_1_VSW_SHIFT)
+((CN_LCD_SIZE_Y -1)<< CN_LCDC_RASTER_TIMING_1_LPP_SHIFT);
g_ptLcdcReg->RASTER_TIMING_2 =
(CN_LCDC_RASTER_TIMING_2_IPC_RISING << CN_LCDC_RASTER_TIMING_2_IPC_SHIFT);
g_ptLcdcReg->LCDDMA_CTRL = 0x00000540;
// Frame buffer start
g_ptLcdcReg->LCDDMA_FB0_BASE = (u32)(u8g_dsp_buffer - CN_PALETTE_SIZE);
// Frame buffer end,不知为何要减1
g_ptLcdcReg->LCDDMA_FB0_CEILING = (u32)(u8g_dsp_buffer + cn_frame_buffer_size - 1);
g_ptLcdcReg->RASTER_CTRL |= 0x00000001; // Enable controller
#endif
return;
}
