static void
doTxSingleDMA(const uint8* data, uint32 count)
{
// Prepare DMA transfer
dmaInProgress = 1;
trace(trace_doTxSingleDMA);
CyDmaTdSetConfiguration(
scsiDmaTxTd[0],
count,
CY_DMA_DISABLE_TD, // Disable the DMA channel when TD completes count bytes
TD_INC_SRC_ADR |
SCSI_TX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete
);
CyDmaTdSetAddress(
scsiDmaTxTd[0],
LO16((uint32)data),
LO16((uint32)scsiTarget_datapath__F0_REG));
CyDmaChSetInitialTd(scsiDmaTxChan, scsiDmaTxTd[0]);
// The DMA controller is a bit trigger-happy. It will retain
// a drq request that was triggered while the channel was
// disabled.
CyDmaClearPendingDrq(scsiDmaTxChan);
scsiTxDMAComplete = 0;
scsiRxDMAComplete = 1;
CyDmaChEnable(scsiDmaTxChan, 1);
}
static void DMA_Start()
{
*(reg8*)Camera_FIFO_dp__F0_REG;
*(reg8*)Camera_FIFO_dp__F0_REG;
*(reg8*)Camera_FIFO_dp__F0_REG;
*(reg8*)Camera_FIFO_dp__F0_REG; //clear fifo
CyDmaClearPendingDrq(DMA_channel); //invalidate pending requests
CyDmaChSetInitialTd(DMA_channel,DMA_TD[0]); //set initial TD
CyDmaChEnable(DMA_channel,1); //enable channel (start streaming)
}
/*******************************************************************************
* Function Name: OSC1_ADC_SAR_Enable
********************************************************************************
*
* Summary:
* Enables DMA channels, address selection counter and FSM of Base component
*
* Parameters:
* None.
*
* Return:
* None.
*
* Side Effects:
* None.
*
* Reentrant:
* No.
*
*******************************************************************************/
void OSC1_ADC_SAR_Enable(void)
{
uint8 enableInterrupts;
static int16 OSC1_ADC_SAR_tempArray[OSC1_ADC_SAR_NUMBER_OF_CHANNELS];
(void)CyDmaClearPendingDrq(OSC1_ADC_SAR_tempChan);
(void)CyDmaClearPendingDrq(OSC1_ADC_SAR_finalChan);
/* Provides initialization procedure for the TempBuf DMA
* Configure this Td as follows:
* - The TD is looping on itself
* - Increment the destination address, but not the source address
*/
if (OSC1_ADC_SAR_tempTD == DMA_INVALID_TD)
{
OSC1_ADC_SAR_tempTD = CyDmaTdAllocate();
}
(void) CyDmaTdSetConfiguration(OSC1_ADC_SAR_tempTD, OSC1_ADC_SAR_TEMP_TRANSFER_COUNT,
OSC1_ADC_SAR_tempTD, ((uint8)OSC1_ADC_SAR_TempBuf__TD_TERMOUT_EN | (uint8)TD_INC_DST_ADR));
/* From the SAR to the TempArray */
(void) CyDmaTdSetAddress(OSC1_ADC_SAR_tempTD, (uint16)(LO16((uint32)OSC1_ADC_SAR_SAR_DATA_ADDR_0)),
(uint16)(LO16((uint32)OSC1_ADC_SAR_tempArray)));
/* Associate the TD with the channel */
(void) CyDmaChSetInitialTd(OSC1_ADC_SAR_tempChan, OSC1_ADC_SAR_tempTD);
/* Provides initialization procedure for the FinalBuf DMA
* Configure this Td as follows:
* - The TD is looping on itself
* - Increment the source and destination address
*/
if (OSC1_ADC_SAR_finalTD == DMA_INVALID_TD)
{
OSC1_ADC_SAR_finalTD = CyDmaTdAllocate();
}
(void) CyDmaTdSetConfiguration(OSC1_ADC_SAR_finalTD, (OSC1_ADC_SAR_FINAL_BYTES_PER_BURST),
OSC1_ADC_SAR_finalTD, ((uint8)(OSC1_ADC_SAR_FinalBuf__TD_TERMOUT_EN) | (uint8)TD_INC_SRC_ADR |
(uint8)TD_INC_DST_ADR));
/* From the the TempArray to Final Array */
(void) CyDmaTdSetAddress(OSC1_ADC_SAR_finalTD, (uint16)(LO16((uint32)OSC1_ADC_SAR_tempArray)),
(uint16)(LO16((uint32)OSC1_ADC_SAR_finalArray)));
/* Associate the TD with the channel */
(void) CyDmaChSetInitialTd(OSC1_ADC_SAR_finalChan, OSC1_ADC_SAR_finalTD);
(void) CyDmaChEnable(OSC1_ADC_SAR_tempChan, 1u);
(void) CyDmaChEnable(OSC1_ADC_SAR_finalChan, 1u);
/* Enable Counter and give Enable pulse to set an address of the last channel */
enableInterrupts = CyEnterCriticalSection();
OSC1_ADC_SAR_CYCLE_COUNTER_AUX_CONTROL_REG |= ((uint8)(OSC1_ADC_SAR_CYCLE_COUNTER_ENABLE));
CyExitCriticalSection(enableInterrupts);
/* Enable FSM of the Base Component */
OSC1_ADC_SAR_CONTROL_REG |= ((uint8)(OSC1_ADC_SAR_BASE_COMPONENT_ENABLE));
OSC1_ADC_SAR_CONTROL_REG |= ((uint8)(OSC1_ADC_SAR_LOAD_COUNTER_PERIOD));
#if(OSC1_ADC_SAR_IRQ_REMOVE == 0u)
/* Clear a pending interrupt */
CyIntClearPending(OSC1_ADC_SAR_INTC_NUMBER);
#endif /* End OSC1_ADC_SAR_IRQ_REMOVE */
}
/*******************************************************************************
* Function Name: USBFS_1_LoadInEP
********************************************************************************
*
* Summary:
* Loads and enables the specified USB data endpoint for an IN interrupt or bulk
* transfer.
*
* Parameters:
* epNumber: Contains the data endpoint number.
* Valid values are between 1 and 8.
* *pData: A pointer to a data array from which the data for the endpoint space
* is loaded.
* length: The number of bytes to transfer from the array and then send as a
* result of an IN request. Valid values are between 0 and 512.
*
* Return:
* None.
*
* Reentrant:
* No.
*
*******************************************************************************/
void USBFS_1_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
{
uint8 ri;
reg8 *p;
#if(USBFS_1_EP_MM == USBFS_1__EP_MANUAL)
uint16 i;
#endif /* End USBFS_1_EP_MM == USBFS_1__EP_MANUAL */
if((epNumber > USBFS_1_EP0) && (epNumber < USBFS_1_MAX_EP))
{
ri = ((epNumber - USBFS_1_EP1) << USBFS_1_EPX_CNTX_ADDR_SHIFT);
p = (reg8 *)(USBFS_1_ARB_RW1_DR_IND + ri);
#if(USBFS_1_EP_MM != USBFS_1__EP_DMAAUTO)
/* Limits length to available buffer space, auto MM could send packets up to 1024 bytes */
if(length > (USBFS_1_EPX_DATA_BUF_MAX - USBFS_1_EP[epNumber].buffOffset))
{
length = USBFS_1_EPX_DATA_BUF_MAX - USBFS_1_EP[epNumber].buffOffset;
}
#endif /* End USBFS_1_EP_MM != USBFS_1__EP_DMAAUTO */
/* Set the count and data toggle */
CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CNT0_IND + ri),
(length >> 8u) | (USBFS_1_EP[epNumber].epToggle));
CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CNT1_IND + ri), length & 0xFFu);
#if(USBFS_1_EP_MM == USBFS_1__EP_MANUAL)
if(pData != NULL)
{
/* Copy the data using the arbiter data register */
for (i = 0u; i < length; i++)
{
CY_SET_REG8(p, pData[i]);
}
}
USBFS_1_EP[epNumber].apiEpState = USBFS_1_NO_EVENT_PENDING;
/* Write the Mode register */
CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + ri), USBFS_1_EP[epNumber].epMode);
#else
/* Init DMA if it was not initialized */
if(USBFS_1_DmaTd[epNumber] == DMA_INVALID_TD)
{
USBFS_1_InitEP_DMA(epNumber, pData);
}
#endif /* End USBFS_1_EP_MM == USBFS_1__EP_MANUAL */
#if(USBFS_1_EP_MM == USBFS_1__EP_DMAMANUAL)
USBFS_1_EP[epNumber].apiEpState = USBFS_1_NO_EVENT_PENDING;
if((pData != NULL) && (length > 0u))
{
/* Enable DMA in mode2 for transferring data */
(void) CyDmaChDisable(USBFS_1_DmaChan[epNumber]);
(void) CyDmaTdSetConfiguration(USBFS_1_DmaTd[epNumber], length, CY_DMA_DISABLE_TD,
TD_TERMIN_EN | TD_INC_SRC_ADR);
(void) CyDmaTdSetAddress(USBFS_1_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p));
/* Enable the DMA */
(void) CyDmaChSetInitialTd(USBFS_1_DmaChan[epNumber], USBFS_1_DmaTd[epNumber]);
(void) CyDmaChEnable(USBFS_1_DmaChan[epNumber], 1u);
/* Generate DMA request */
* (reg8 *)(USBFS_1_ARB_EP1_CFG_IND + ri) |= USBFS_1_ARB_EPX_CFG_DMA_REQ;
* (reg8 *)(USBFS_1_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_1_ARB_EPX_CFG_DMA_REQ));
/* Mode register will be written in arb ISR after DMA transfer complete */
}
else
{
/* When zero-length packet - write the Mode register directly */
CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + ri), USBFS_1_EP[epNumber].epMode);
}
#endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAMANUAL */
#if(USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO)
if(pData != NULL)
{
/* Enable DMA in mode3 for transferring data */
(void) CyDmaChDisable(USBFS_1_DmaChan[epNumber]);
(void) CyDmaTdSetConfiguration(USBFS_1_DmaTd[epNumber], length,
USBFS_1_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);
(void) CyDmaTdSetAddress(USBFS_1_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p));
/* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */
(void) CyDmaClearPendingDrq(USBFS_1_DmaChan[epNumber]);
/* Enable the DMA */
(void) CyDmaChSetInitialTd(USBFS_1_DmaChan[epNumber], USBFS_1_DmaTd[epNumber]);
(void) CyDmaChEnable(USBFS_1_DmaChan[epNumber], 1u);
}
else
{
USBFS_1_EP[epNumber].apiEpState = USBFS_1_NO_EVENT_PENDING;
if(length > 0u)
{
/* Set Data ready status, This will generate DMA request */
* (reg8 *)(USBFS_1_ARB_EP1_CFG_IND + ri) |= USBFS_1_ARB_EPX_CFG_IN_DATA_RDY;
/* Mode register will be written in arb ISR(In Buffer Full) after first DMA transfer complete */
}
else
{
/* When zero-length packet - write the Mode register directly */
CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + ri), USBFS_1_EP[epNumber].epMode);
}
}
#endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO */
}
void main_fsm_10kHz(void)
{
uint8 i = 0;
unsigned char result = 0;
//RS-485 Byte Input
#ifdef USE_RS485
//Data received via DMA
if(data_ready_485)
{
data_ready_485 = 0;
//Got new data in, try to decode
cmd_ready_485 = unpack_payload_485();
}
#endif //USE_RS485
//USB Byte Input
#ifdef USE_USB
get_usb_data();
if(data_ready_usb)
{
data_ready_usb = 0;
//Got new data in, try to decode
cmd_ready_usb = unpack_payload_usb();
eL1 = 1;
}
#endif //USE_USB
//FlexSEA Network Communication
#ifdef USE_COMM
//Valid communication from RS-485?
if(cmd_ready_485 != 0)
{
cmd_ready_485 = 0;
//Cheap trick to get first line //ToDo: support more than 1
for(i = 0; i < PAYLOAD_BUF_LEN; i++)
{
tmp_rx_command_485[i] = rx_command_485[0][i];
}
//payload_parse_str() calls the functions (if valid)
result = payload_parse_str(tmp_rx_command_485);
//LED:
if(result == PARSE_SUCCESSFUL)
{
//Green LED only if the ID matched and the command was known
new_cmd_led = 1;
}
//Test ToDo remove
CyDmaClearPendingDrq(DMA_3_Chan);
}
//Time to reply - RS-485?
if(reply_ready_flag)
{
//We never replied in the same time slot:
if(t1_time_share != reply_ready_timestamp)
{
rs485_puts(reply_ready_buf, reply_ready_len);
reply_ready_flag = 0;
}
}
//Valid communication from USB?
if(cmd_ready_usb != 0)
{
cmd_ready_usb = 0;
//Cheap trick to get first line //ToDo: support more than 1
for(i = 0; i < PAYLOAD_BUF_LEN; i++)
{
tmp_rx_command_usb[i] = rx_command_usb[0][i];
}
//payload_parse_str() calls the functions (if valid)
result = payload_parse_str(tmp_rx_command_usb);
//LED:
if(result == PARSE_SUCCESSFUL)
{
//Green LED only if the ID matched and the command was known
new_cmd_led = 1;
}
}
#endif //USE_COMM
#ifdef USE_SPI_COMMUT
#if(ENC_COMMUT == ENC_AS5047)
sensor_commut_1();
#endif //ENC_AS5047
#endif
}