/* see if an analog VGA monitor is connected to connector #2 */
bool eng_dac2_crt_connected()
{
uint32 output, dac;
bool present;
/* NOTE:
* NV11 can't do this: It will report DAC1 status instead because it HAS no
* actual secondary DAC function. */
/* (It DOES have a secondary palette RAM and pixelclock PLL though.) */
/* save output connector setting */
output = DAC2R(OUTPUT);
/* save DAC state */
dac = DAC2R(TSTCTRL);
/* turn on DAC2 */
DAC2W(TSTCTRL, (DAC2R(TSTCTRL) & 0xfffeffff));
/* select primary head and turn off CRT (and DVI?) outputs */
DAC2W(OUTPUT, (output & 0x0000feee));
/* wait for signal lines to stabilize */
snooze(1000);
/* re-enable CRT output */
DAC2W(OUTPUT, (DAC2R(OUTPUT) | 0x00000001));
/* setup RGB test signal levels to approx 30% of DAC range and enable them
* (NOTE: testsignal function block resides in DAC1 only (!)) */
DACW(TSTDATA, ((0x2 << 30) | (0x140 << 20) | (0x140 << 10) | (0x140 << 0)));
/* route test signals to output
* (NOTE: testsignal function block resides in DAC1 only (!)) */
DACW(TSTCTRL, (DACR(TSTCTRL) | 0x00001000));
/* wait for signal lines to stabilize */
snooze(1000);
/* do actual detection: all signals paths high == CRT connected */
if (DAC2R(TSTCTRL) & 0x10000000)
{
present = true;
LOG(4,("DAC2: CRT detected on connector #2\n"));
}
else
{
present = false;
LOG(4,("DAC2: no CRT detected on connector #2\n"));
}
/* kill test signal routing
* (NOTE: testsignal function block resides in DAC1 only (!)) */
DACW(TSTCTRL, (DACR(TSTCTRL) & 0xffffefff));
/* restore output connector setting */
DAC2W(OUTPUT, output);
/* restore DAC state */
DAC2W(TSTCTRL, dac);
return present;
}
static void pinsnv30_arch_fake(void)
{
/* determine PLL type */
LOG(8,("INFO: NV30 architecture chip, PIXPLLC2 DAC1 = $%08x, DAC2 = $%08x\n",
DACR(PIXPLLC2), DAC2R(PIXPLLC2)));
switch (si->ps.card_type)
{
case NV31:
case NV36:
case NV40:
/* we have a extended PLL */
si->ps.ext_pll = true;
break;
default:
/* we have a standard PLL */
si->ps.ext_pll = false;
break;
}
/* carefull not to take to high limits, and high should be >= 2x low. */
si->ps.max_system_vco = 350;
si->ps.min_system_vco = 128;
si->ps.max_pixel_vco = 350;
si->ps.min_pixel_vco = 128;
si->ps.max_video_vco = 350;
si->ps.min_video_vco = 128;
si->ps.max_dac1_clock = 350;
si->ps.max_dac1_clock_8 = 350;
si->ps.max_dac1_clock_16 = 350;
/* 'failsave' values */
si->ps.max_dac1_clock_24 = 320;
si->ps.max_dac1_clock_32 = 280;
si->ps.max_dac1_clock_32dh = 250;
/* secondary head */
/* GeForceFX cards have dual integrated DACs with identical capaability */
/* (called nview technology) */
si->ps.max_dac2_clock = 350;
si->ps.max_dac2_clock_8 = 350;
si->ps.max_dac2_clock_16 = 350;
/* 'failsave' values */
si->ps.max_dac2_clock_24 = 320;
si->ps.max_dac2_clock_32 = 280;
si->ps.max_dac2_clock_32dh = 250;
//fixme: primary & secondary_dvi should be overrule-able via skel.settings
si->ps.primary_dvi = false;
si->ps.secondary_dvi = false;
/* not used (yet) because no coldstart will be attempted (yet) */
si->ps.std_engine_clock = 190;
si->ps.std_memory_clock = 190;
}
static void detect_panels()
{
/* detect if the BIOS enabled LCD's (internal panels or DVI) or TVout */
/* both external TMDS transmitters (used for LCD/DVI) and external TVencoders
* (can) use the CRTC's in slaved mode. */
/* Note:
* DFP's are programmed with standard VESA modelines by the card's BIOS! */
bool slaved_for_dev1 = false, slaved_for_dev2 = false;
bool tvout1 = false, tvout2 = false;
/* check primary head: */
/* enable access to primary head */
set_crtc_owner(0);
/* unlock head's registers for R/W access */
CRTCW(LOCK, 0x57);
CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));
LOG(2,("INFO: Dumping flatpanel related CRTC registers:\n"));
/* related info PIXEL register:
* b7: 1 = slaved mode (all cards). */
LOG(2,("CRTC1: PIXEL register: $%02x\n", CRTCR(PIXEL)));
/* info LCD register:
* b7: 1 = stereo view (shutter glasses use) (all cards),
* b5: 1 = power ext. TMDS (or something)/0 = TVout use (?) (confirmed NV17, NV28),
* b4: 1 = power ext. TMDS (or something)/0 = TVout use (?) (confirmed NV34),
* b3: 1 = ??? (not panel related probably!) (confirmed NV34),
* b1: 1 = power ext. TMDS (or something) (?) (confirmed NV05?, NV17),
* b0: 1 = select panel encoder / 0 = select TVout encoder (all cards). */
LOG(2,("CRTC1: LCD register: $%02x\n", CRTCR(LCD)));
/* info 0x59 register:
* b0: 1 = enable ext. TMDS clock (DPMS) (confirmed NV28, NV34). */
LOG(2,("CRTC1: register $59: $%02x\n", CRTCR(0x59)));
/* info 0x9f register:
* b4: 0 = TVout use (?). */
LOG(2,("CRTC1: register $9f: $%02x\n", CRTCR(0x9f)));
/* detect active slave device (if any) */
slaved_for_dev1 = (CRTCR(PIXEL) & 0x80);
if (slaved_for_dev1)
{
/* if the panel isn't selected, tvout is.. */
tvout1 = !(CRTCR(LCD) & 0x01);
}
if (si->ps.secondary_head)
{
/* check secondary head: */
/* enable access to secondary head */
set_crtc_owner(1);
/* unlock head's registers for R/W access */
CRTC2W(LOCK, 0x57);
CRTC2W(VSYNCE ,(CRTC2R(VSYNCE) & 0x7f));
LOG(2,("CRTC2: PIXEL register: $%02x\n", CRTC2R(PIXEL)));
LOG(2,("CRTC2: LCD register: $%02x\n", CRTC2R(LCD)));
LOG(2,("CRTC2: register $59: $%02x\n", CRTC2R(0x59)));
LOG(2,("CRTC2: register $9f: $%02x\n", CRTC2R(0x9f)));
/* detect active slave device (if any) */
slaved_for_dev2 = (CRTC2R(PIXEL) & 0x80);
if (slaved_for_dev2)
{
/* if the panel isn't selected, tvout is.. */
tvout2 = !(CRTC2R(LCD) & 0x01);
}
}
LOG(2,("INFO: End flatpanel related CRTC registers dump.\n"));
/* do some presets */
si->ps.p1_timing.h_display = 0;
si->ps.p1_timing.v_display = 0;
si->ps.panel1_aspect = 0;
si->ps.p2_timing.h_display = 0;
si->ps.p2_timing.v_display = 0;
si->ps.panel2_aspect = 0;
si->ps.slaved_tmds1 = false;
si->ps.slaved_tmds2 = false;
si->ps.master_tmds1 = false;
si->ps.master_tmds2 = false;
si->ps.tmds1_active = false;
si->ps.tmds2_active = false;
/* determine the situation we are in... (regarding flatpanels) */
/* fixme: add VESA DDC EDID stuff one day... */
/* fixme: find out how to program those transmitters one day instead of
* relying on the cards BIOS to do it. This adds TVout options where panels
* are used!
* Currently we'd loose the panel setup while not being able to restore it. */
/* note: (facts)
* -> NV11 and NV17 laptops have LVDS panels, programmed in both sets registers;
* -> NV34 laptops have TMDS panels, programmed in only one set of registers;
* -> NV11, NV25 and NV34 DVI cards, so external panels (TMDS) are programmed
* in only one set of registers;
* -> a register-set's FP_TG_CTRL register, bit 31 tells you if a LVDS panel is
* connected to the primary head (0), or to the secondary head (1) except
* on some NV11's if this bit is '0' there;
* -> for LVDS panels both registersets are programmed identically by the card's
* BIOSes;
* -> the programmed set of registers tells you where a TMDS (DVI) panel is
* connected;
* -> On all cards a CRTC is used in slaved mode when a panel is connected,
* except on NV11: here master mode is (might be?) detected. */
/* note also:
* external TMDS encoders are only used for logic-level translation: it's
* modeline registers are not used. Instead the GPU's internal modeline registers
* are used. The external encoder is not connected to a I2C bus (confirmed NV34). */
if (slaved_for_dev1 && !tvout1)
{
uint16 width = ((DACR(FP_HDISPEND) & 0x0000ffff) + 1);
uint16 height = ((DACR(FP_VDISPEND) & 0x0000ffff) + 1);
if ((width >= 640) && (height >= 480))
{
si->ps.slaved_tmds1 = true;
si->ps.tmds1_active = true;
si->ps.p1_timing.h_display = width;
si->ps.p1_timing.v_display = height;
}
}
if (si->ps.secondary_head && slaved_for_dev2 && !tvout2)
{
uint16 width = ((DAC2R(FP_HDISPEND) & 0x0000ffff) + 1);
uint16 height = ((DAC2R(FP_VDISPEND) & 0x0000ffff) + 1);
if ((width >= 640) && (height >= 480))
{
si->ps.slaved_tmds2 = true;
si->ps.tmds2_active = true;
si->ps.p2_timing.h_display = width;
si->ps.p2_timing.v_display = height;
}
}
if ((si->ps.card_type == NV11) &&
!si->ps.slaved_tmds1 && !tvout1)
{
uint16 width = ((DACR(FP_HDISPEND) & 0x0000ffff) + 1);
uint16 height = ((DACR(FP_VDISPEND) & 0x0000ffff) + 1);
if ((width >= 640) && (height >= 480))
{
si->ps.master_tmds1 = true;
si->ps.tmds1_active = true;
si->ps.p1_timing.h_display = width;
si->ps.p1_timing.v_display = height;
}
}
if ((si->ps.card_type == NV11) &&
si->ps.secondary_head && !si->ps.slaved_tmds2 && !tvout2)
{
uint16 width = ((DAC2R(FP_HDISPEND) & 0x0000ffff) + 1);
uint16 height = ((DAC2R(FP_VDISPEND) & 0x0000ffff) + 1);
if ((width >= 640) && (height >= 480))
{
si->ps.master_tmds2 = true;
si->ps.tmds2_active = true;
si->ps.p2_timing.h_display = width;
si->ps.p2_timing.v_display = height;
}
}
//fixme...:
//we are assuming that no DVI is used as external monitor on laptops;
//otherwise we probably get into trouble here if the checked specs match.
if (si->ps.laptop && si->ps.tmds1_active && si->ps.tmds2_active &&
((DACR(FP_TG_CTRL) & 0x80000000) == (DAC2R(FP_TG_CTRL) & 0x80000000)) &&
(si->ps.p1_timing.h_display == si->ps.p2_timing.h_display) &&
(si->ps.p1_timing.v_display == si->ps.p2_timing.v_display))
{
LOG(2,("INFO: correcting double detection of single panel!\n"));
if (si->ps.card_type == NV11)
{
/* LVDS panel is _always_ on CRTC2, so clear false primary detection */
si->ps.slaved_tmds1 = false;
si->ps.master_tmds1 = false;
si->ps.tmds1_active = false;
si->ps.p1_timing.h_display = 0;
si->ps.p1_timing.v_display = 0;
}
else
{
if (DACR(FP_TG_CTRL) & 0x80000000)
{
/* LVDS panel is on CRTC2, so clear false primary detection */
si->ps.slaved_tmds1 = false;
si->ps.master_tmds1 = false;
si->ps.tmds1_active = false;
si->ps.p1_timing.h_display = 0;
si->ps.p1_timing.v_display = 0;
}
else
{
/* LVDS panel is on CRTC1, so clear false secondary detection */
si->ps.slaved_tmds2 = false;
si->ps.master_tmds2 = false;
si->ps.tmds2_active = false;
si->ps.p2_timing.h_display = 0;
si->ps.p2_timing.v_display = 0;
}
}
}
/* fetch panel(s) modeline(s) */
if (si->ps.tmds1_active)
{
/* determine panel aspect ratio */
si->ps.panel1_aspect =
(si->ps.p1_timing.h_display / ((float)si->ps.p1_timing.v_display));
/* horizontal timing */
si->ps.p1_timing.h_sync_start = (DACR(FP_HSYNC_S) & 0x0000ffff) + 1;
si->ps.p1_timing.h_sync_end = (DACR(FP_HSYNC_E) & 0x0000ffff) + 1;
si->ps.p1_timing.h_total = (DACR(FP_HTOTAL) & 0x0000ffff) + 1;
/* vertical timing */
si->ps.p1_timing.v_sync_start = (DACR(FP_VSYNC_S) & 0x0000ffff) + 1;
si->ps.p1_timing.v_sync_end = (DACR(FP_VSYNC_E) & 0x0000ffff) + 1;
si->ps.p1_timing.v_total = (DACR(FP_VTOTAL) & 0x0000ffff) + 1;
/* sync polarity */
si->ps.p1_timing.flags = 0;
if (DACR(FP_TG_CTRL) & 0x00000001) si->ps.p1_timing.flags |= B_POSITIVE_VSYNC;
if (DACR(FP_TG_CTRL) & 0x00000010) si->ps.p1_timing.flags |= B_POSITIVE_HSYNC;
/* refreshrate:
* fix a DVI or laptop flatpanel to 60Hz refresh! */
si->ps.p1_timing.pixel_clock =
(si->ps.p1_timing.h_total * si->ps.p1_timing.v_total * 60) / 1000;
}
if (si->ps.tmds2_active)
{
/* determine panel aspect ratio */
si->ps.panel2_aspect =
(si->ps.p2_timing.h_display / ((float)si->ps.p2_timing.v_display));
/* horizontal timing */
si->ps.p2_timing.h_sync_start = (DAC2R(FP_HSYNC_S) & 0x0000ffff) + 1;
si->ps.p2_timing.h_sync_end = (DAC2R(FP_HSYNC_E) & 0x0000ffff) + 1;
si->ps.p2_timing.h_total = (DAC2R(FP_HTOTAL) & 0x0000ffff) + 1;
/* vertical timing */
si->ps.p2_timing.v_sync_start = (DAC2R(FP_VSYNC_S) & 0x0000ffff) + 1;
si->ps.p2_timing.v_sync_end = (DAC2R(FP_VSYNC_E) & 0x0000ffff) + 1;
si->ps.p2_timing.v_total = (DAC2R(FP_VTOTAL) & 0x0000ffff) + 1;
/* sync polarity */
si->ps.p2_timing.flags = 0;
if (DAC2R(FP_TG_CTRL) & 0x00000001) si->ps.p2_timing.flags |= B_POSITIVE_VSYNC;
if (DAC2R(FP_TG_CTRL) & 0x00000010) si->ps.p2_timing.flags |= B_POSITIVE_HSYNC;
/* refreshrate:
* fix a DVI or laptop flatpanel to 60Hz refresh! */
si->ps.p2_timing.pixel_clock =
(si->ps.p2_timing.h_total * si->ps.p2_timing.v_total * 60) / 1000;
}
/* dump some panel configuration registers... */
LOG(2,("INFO: Dumping flatpanel registers:\n"));
LOG(2,("DUALHEAD_CTRL: $%08x\n", ENG_REG32(RG32_DUALHEAD_CTRL)));
LOG(2,("DAC1: FP_HDISPEND: %d\n", DACR(FP_HDISPEND)));
LOG(2,("DAC1: FP_HTOTAL: %d\n", DACR(FP_HTOTAL)));
LOG(2,("DAC1: FP_HCRTC: %d\n", DACR(FP_HCRTC)));
LOG(2,("DAC1: FP_HSYNC_S: %d\n", DACR(FP_HSYNC_S)));
LOG(2,("DAC1: FP_HSYNC_E: %d\n", DACR(FP_HSYNC_E)));
LOG(2,("DAC1: FP_HVALID_S: %d\n", DACR(FP_HVALID_S)));
LOG(2,("DAC1: FP_HVALID_E: %d\n", DACR(FP_HVALID_E)));
LOG(2,("DAC1: FP_VDISPEND: %d\n", DACR(FP_VDISPEND)));
LOG(2,("DAC1: FP_VTOTAL: %d\n", DACR(FP_VTOTAL)));
LOG(2,("DAC1: FP_VCRTC: %d\n", DACR(FP_VCRTC)));
LOG(2,("DAC1: FP_VSYNC_S: %d\n", DACR(FP_VSYNC_S)));
LOG(2,("DAC1: FP_VSYNC_E: %d\n", DACR(FP_VSYNC_E)));
LOG(2,("DAC1: FP_VVALID_S: %d\n", DACR(FP_VVALID_S)));
LOG(2,("DAC1: FP_VVALID_E: %d\n", DACR(FP_VVALID_E)));
LOG(2,("DAC1: FP_CHKSUM: $%08x = (dec) %d\n", DACR(FP_CHKSUM),DACR(FP_CHKSUM)));
LOG(2,("DAC1: FP_TST_CTRL: $%08x\n", DACR(FP_TST_CTRL)));
LOG(2,("DAC1: FP_TG_CTRL: $%08x\n", DACR(FP_TG_CTRL)));
LOG(2,("DAC1: FP_DEBUG0: $%08x\n", DACR(FP_DEBUG0)));
LOG(2,("DAC1: FP_DEBUG1: $%08x\n", DACR(FP_DEBUG1)));
LOG(2,("DAC1: FP_DEBUG2: $%08x\n", DACR(FP_DEBUG2)));
LOG(2,("DAC1: FP_DEBUG3: $%08x\n", DACR(FP_DEBUG3)));
LOG(2,("DAC1: FUNCSEL: $%08x\n", ENG_REG32(RG32_FUNCSEL)));
LOG(2,("DAC1: PANEL_PWR: $%08x\n", ENG_REG32(RG32_PANEL_PWR)));
if(si->ps.secondary_head)
{
LOG(2,("DAC2: FP_HDISPEND: %d\n", DAC2R(FP_HDISPEND)));
LOG(2,("DAC2: FP_HTOTAL: %d\n", DAC2R(FP_HTOTAL)));
LOG(2,("DAC2: FP_HCRTC: %d\n", DAC2R(FP_HCRTC)));
LOG(2,("DAC2: FP_HSYNC_S: %d\n", DAC2R(FP_HSYNC_S)));
LOG(2,("DAC2: FP_HSYNC_E: %d\n", DAC2R(FP_HSYNC_E)));
LOG(2,("DAC2: FP_HVALID_S:%d\n", DAC2R(FP_HVALID_S)));
LOG(2,("DAC2: FP_HVALID_E: %d\n", DAC2R(FP_HVALID_E)));
LOG(2,("DAC2: FP_VDISPEND: %d\n", DAC2R(FP_VDISPEND)));
LOG(2,("DAC2: FP_VTOTAL: %d\n", DAC2R(FP_VTOTAL)));
LOG(2,("DAC2: FP_VCRTC: %d\n", DAC2R(FP_VCRTC)));
LOG(2,("DAC2: FP_VSYNC_S: %d\n", DAC2R(FP_VSYNC_S)));
LOG(2,("DAC2: FP_VSYNC_E: %d\n", DAC2R(FP_VSYNC_E)));
LOG(2,("DAC2: FP_VVALID_S: %d\n", DAC2R(FP_VVALID_S)));
LOG(2,("DAC2: FP_VVALID_E: %d\n", DAC2R(FP_VVALID_E)));
LOG(2,("DAC2: FP_CHKSUM: $%08x = (dec) %d\n", DAC2R(FP_CHKSUM),DAC2R(FP_CHKSUM)));
LOG(2,("DAC2: FP_TST_CTRL: $%08x\n", DAC2R(FP_TST_CTRL)));
LOG(2,("DAC2: FP_TG_CTRL: $%08x\n", DAC2R(FP_TG_CTRL)));
LOG(2,("DAC2: FP_DEBUG0: $%08x\n", DAC2R(FP_DEBUG0)));
LOG(2,("DAC2: FP_DEBUG1: $%08x\n", DAC2R(FP_DEBUG1)));
LOG(2,("DAC2: FP_DEBUG2: $%08x\n", DAC2R(FP_DEBUG2)));
LOG(2,("DAC2: FP_DEBUG3: $%08x\n", DAC2R(FP_DEBUG3)));
LOG(2,("DAC2: FUNCSEL: $%08x\n", ENG_REG32(RG32_2FUNCSEL)));
LOG(2,("DAC2: PANEL_PWR: $%08x\n", ENG_REG32(RG32_2PANEL_PWR)));
}
LOG(2,("INFO: End flatpanel registers dump.\n"));
}
