int board_init(void)
{
unsigned int temp;
#ifndef CONFIG_USE_IRQ
irq_init();
#endif
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_LCDK;
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
/* setup the SUSPSRC for ARM to control emulation suspend */
writel(readl(&davinci_syscfg_regs->suspsrc) &
~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
DAVINCI_SYSCFG_SUSPSRC_UART2),
&davinci_syscfg_regs->suspsrc);
/* configure pinmux settings */
if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
return 1;
#ifdef CONFIG_NAND_DAVINCI
/*
* NAND CS setup - cycle counts based on da850evm NAND timings in the
* Linux kernel @ 25MHz EMIFA
*/
writel((DAVINCI_ABCR_WSETUP(15) |
DAVINCI_ABCR_WSTROBE(63) |
DAVINCI_ABCR_WHOLD(7) |
DAVINCI_ABCR_RSETUP(15) |
DAVINCI_ABCR_RSTROBE(63) |
DAVINCI_ABCR_RHOLD(7) |
DAVINCI_ABCR_TA(3) |
DAVINCI_ABCR_ASIZE_16BIT),
&davinci_emif_regs->ab2cr); /* CS3 */
#endif
#ifdef CONFIG_DAVINCI_MMC
if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0)
return 1;
#endif
#ifdef CONFIG_DRIVER_TI_EMAC
if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
return 1;
davinci_emac_mii_mode_sel(HAS_RMII);
#endif /* CONFIG_DRIVER_TI_EMAC */
/* enable the console UART */
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
DAVINCI_UART_PWREMU_MGMT_UTRST),
&davinci_uart2_ctrl_regs->pwremu_mgmt);
return 0;
}
int board_init(void)
{
#ifndef CONFIG_USE_IRQ
irq_init();
#endif
#ifdef CONFIG_NAND_DAVINCI
/* EMIFA 100MHz clock select */
writel(readl(&davinci_syscfg_regs->cfgchip3) & ~2,
&davinci_syscfg_regs->cfgchip3);
/* NAND CS setup */
writel((DAVINCI_ABCR_WSETUP(0) |
DAVINCI_ABCR_WSTROBE(2) |
DAVINCI_ABCR_WHOLD(0) |
DAVINCI_ABCR_RSETUP(0) |
DAVINCI_ABCR_RSTROBE(2) |
DAVINCI_ABCR_RHOLD(0) |
DAVINCI_ABCR_TA(2) |
DAVINCI_ABCR_ASIZE_8BIT),
&davinci_emif_regs->ab2cr);
#endif
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA830_EVM;
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
/*
* Power on required peripherals
* ARM does not have access by default to PSC0 and PSC1
* assuming here that the DSP bootloader has set the IOPU
* such that PSC access is available to ARM
*/
if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
return 1;
/* setup the SUSPSRC for ARM to control emulation suspend */
writel(readl(&davinci_syscfg_regs->suspsrc) &
~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
DAVINCI_SYSCFG_SUSPSRC_SPI0 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
DAVINCI_SYSCFG_SUSPSRC_UART2),
&davinci_syscfg_regs->suspsrc);
/* configure pinmux settings */
if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
return 1;
/* enable the console UART */
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
DAVINCI_UART_PWREMU_MGMT_UTRST),
&davinci_uart2_ctrl_regs->pwremu_mgmt);
return(0);
}
int board_init(void)
{
#ifndef CONFIG_USE_IRQ
/*
* Mask all IRQs by clearing the global enable and setting
* the enable clear for all the 90 interrupts.
*/
writel(0, &davinci_aintc_regs->ger);
writel(0, &davinci_aintc_regs->hier);
writel(0xffffffff, &davinci_aintc_regs->ecr1);
writel(0xffffffff, &davinci_aintc_regs->ecr2);
writel(0xffffffff, &davinci_aintc_regs->ecr3);
#endif
#ifdef CONFIG_NAND_DAVINCI
/* EMIFA 100MHz clock select */
writel(readl(&davinci_syscfg_regs->cfgchip3) & ~2,
&davinci_syscfg_regs->cfgchip3);
/* NAND CS setup */
writel((DAVINCI_ABCR_WSETUP(0) |
DAVINCI_ABCR_WSTROBE(2) |
DAVINCI_ABCR_WHOLD(0) |
DAVINCI_ABCR_RSETUP(0) |
DAVINCI_ABCR_RSTROBE(2) |
DAVINCI_ABCR_RHOLD(0) |
DAVINCI_ABCR_TA(2) |
DAVINCI_ABCR_ASIZE_8BIT),
&davinci_emif_regs->AB2CR);
#endif
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA830_EVM;
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
/*
* Power on required peripherals
* ARM does not have access by default to PSC0 and PSC1
* assuming here that the DSP bootloader has set the IOPU
* such that PSC access is available to ARM
*/
lpsc_on(DAVINCI_LPSC_AEMIF); /* NAND, NOR */
lpsc_on(DAVINCI_LPSC_SPI0); /* Serial Flash */
lpsc_on(DAVINCI_LPSC_EMAC); /* image download */
lpsc_on(DAVINCI_LPSC_UART2); /* console */
lpsc_on(DAVINCI_LPSC_GPIO);
/* setup the SUSPSRC for ARM to control emulation suspend */
writel(readl(&davinci_syscfg_regs->suspsrc) &
~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
DAVINCI_SYSCFG_SUSPSRC_SPI0 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
DAVINCI_SYSCFG_SUSPSRC_UART2),
&davinci_syscfg_regs->suspsrc);
/* configure pinmux settings */
if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
return 1;
/* enable the console UART */
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
DAVINCI_UART_PWREMU_MGMT_UTRST),
&davinci_uart2_ctrl_regs->pwremu_mgmt);
return(0);
}
int board_early_init_f(void)
{
/* PinMux for GPIO */
if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
return 1;
/* Set DISP_ON high to enable LCD output*/
gpio_direction_output(97, 1);
/* Set the RESETOUTn low */
gpio_direction_output(111, 0);
/* Set U0_SW0 low for UART0 as console*/
gpio_direction_output(106, 0);
/* Set U0_SW1 low for UART0 as console*/
gpio_direction_output(108, 0);
/* Set LCD_B_PWR low to power down LCD Backlight*/
gpio_direction_output(102, 0);
#ifndef CONFIG_USE_IRQ
irq_init();
#endif
/*
* NAND CS setup - cycle counts based on da850evm NAND timings in the
* Linux kernel @ 25MHz EMIFA
*/
#ifdef CONFIG_NAND_DAVINCI
writel((DAVINCI_ABCR_WSETUP(0) |
DAVINCI_ABCR_WSTROBE(1) |
DAVINCI_ABCR_WHOLD(0) |
DAVINCI_ABCR_RSETUP(0) |
DAVINCI_ABCR_RSTROBE(1) |
DAVINCI_ABCR_RHOLD(0) |
DAVINCI_ABCR_TA(0) |
DAVINCI_ABCR_ASIZE_8BIT),
&davinci_emif_regs->ab1cr); /* CS2 */
#endif
/*
* Power on required peripherals
* ARM does not have access by default to PSC0 and PSC1
* assuming here that the DSP bootloader has set the IOPU
* such that PSC access is available to ARM
*/
if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
return 1;
/* setup the SUSPSRC for ARM to control emulation suspend */
writel(readl(&davinci_syscfg_regs->suspsrc) &
~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
DAVINCI_SYSCFG_SUSPSRC_UART0),
&davinci_syscfg_regs->suspsrc);
/* configure pinmux settings */
if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
return 1;
#ifdef CONFIG_DRIVER_TI_EMAC
if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
return 1;
davinci_emac_mii_mode_sel(HAS_RMII);
#endif /* CONFIG_DRIVER_TI_EMAC */
/* enable the console UART */
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
DAVINCI_UART_PWREMU_MGMT_UTRST),
&davinci_uart0_ctrl_regs->pwremu_mgmt);
/*
* Reconfigure the LCDC priority to the highest to ensure that
* the throughput/latency requirements for the LCDC are met.
*/
writel(readl(&davinci_syscfg_regs->mstpri[2]) & 0x0fffffff,
&davinci_syscfg_regs->mstpri[2]);
return 0;
}
int board_init(void)
{
irq_init();
#ifdef CONFIG_NAND_DAVINCI
/*
* NAND CS setup - cycle counts based on da850evm NAND timings in the
* Linux kernel @ 25MHz EMIFA
*/
writel((DAVINCI_ABCR_WSETUP(2) |
DAVINCI_ABCR_WSTROBE(2) |
DAVINCI_ABCR_WHOLD(1) |
DAVINCI_ABCR_RSETUP(1) |
DAVINCI_ABCR_RSTROBE(4) |
DAVINCI_ABCR_RHOLD(0) |
DAVINCI_ABCR_TA(1) |
DAVINCI_ABCR_ASIZE_8BIT),
&davinci_emif_regs->ab2cr); /* CS3 */
#endif
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
/* setup the SUSPSRC for ARM to control emulation suspend */
writel(readl(&davinci_syscfg_regs->suspsrc) &
~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
DAVINCI_SYSCFG_SUSPSRC_UART2),
&davinci_syscfg_regs->suspsrc);
/* configure pinmux settings */
if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
return 1;
#ifdef CONFIG_USE_NOR
/* Set the GPIO direction as output */
clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
/* Set the output as low */
writel(0x01 << 11, GPIO_BANK0_REG_CLR_ADDR);
#endif
#ifdef CONFIG_MMC_DAVINCI
/* Set the GPIO direction as output */
clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
/* Set the output as high */
writel(0x01 << 11, GPIO_BANK0_REG_SET_ADDR);
#endif
#ifdef CONFIG_DRIVER_TI_EMAC
davinci_emac_mii_mode_sel(HAS_RMII);
#endif /* CONFIG_DRIVER_TI_EMAC */
/* enable the console UART */
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
DAVINCI_UART_PWREMU_MGMT_UTRST),
&davinci_uart2_ctrl_regs->pwremu_mgmt);
return 0;
}
int board_init(void)
{
#ifdef CONFIG_USE_NOR
u32 val;
#endif
#ifndef CONFIG_USE_IRQ
irq_init();
#endif
#ifdef CONFIG_NAND_DAVINCI
/*
* NAND CS setup - cycle counts based on da850evm NAND timings in the
* Linux kernel @ 25MHz EMIFA
*/
writel((DAVINCI_ABCR_WSETUP(0) |
DAVINCI_ABCR_WSTROBE(1) |
DAVINCI_ABCR_WHOLD(0) |
DAVINCI_ABCR_RSETUP(0) |
DAVINCI_ABCR_RSTROBE(1) |
DAVINCI_ABCR_RHOLD(0) |
DAVINCI_ABCR_TA(1) |
DAVINCI_ABCR_ASIZE_8BIT),
&davinci_emif_regs->ab2cr); /* CS3 */
#endif
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
/*
* Power on required peripherals
* ARM does not have access by default to PSC0 and PSC1
* assuming here that the DSP bootloader has set the IOPU
* such that PSC access is available to ARM
*/
if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
return 1;
/* setup the SUSPSRC for ARM to control emulation suspend */
writel(readl(&davinci_syscfg_regs->suspsrc) &
~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
DAVINCI_SYSCFG_SUSPSRC_UART2),
&davinci_syscfg_regs->suspsrc);
/* configure pinmux settings */
if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
return 1;
#ifdef CONFIG_USE_NOR
/* Set the GPIO direction as output */
clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
/* Set the output as low */
val = readl(GPIO_BANK0_REG_SET_ADDR);
val |= (0x01 << 11);
writel(val, GPIO_BANK0_REG_CLR_ADDR);
#endif
#ifdef CONFIG_DRIVER_TI_EMAC
if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
return 1;
davinci_emac_mii_mode_sel(HAS_RMII);
#endif /* CONFIG_DRIVER_TI_EMAC */
/* enable the console UART */
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
DAVINCI_UART_PWREMU_MGMT_UTRST),
&davinci_uart2_ctrl_regs->pwremu_mgmt);
return 0;
}