int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port) { volatile void *mbase = NULL; int attempts = 0; pci_set_ops(hose, pcie_read_config_byte, pcie_read_config_word, pcie_read_config_dword, pcie_write_config_byte, pcie_write_config_word, pcie_write_config_dword); switch (port) { case 0: mbase = (u32 *)CFG_PCIE0_XCFGBASE; hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE; break; case 1: mbase = (u32 *)CFG_PCIE1_XCFGBASE; hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE; break; case 2: mbase = (u32 *)CFG_PCIE2_XCFGBASE; hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE; break; } /* * Set up outbound translation to hose->mem_space from PLB * addresses at an offset of 0xd_0000_0000. We set the low * bits of the mask to 11 to turn off splitting into 8 * subregions and to enable the outbound translation. */ out_le32(mbase + PECFG_POM0LAH, 0x00001ff8); out_le32(mbase + PECFG_POM0LAL, 0x00001000); switch (port) { case 0: mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + port * CFG_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), ~(CFG_PCIE_MEMSIZE - 1) | 3); break; case 1: mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE + port * CFG_PCIE_MEMSIZE)); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), ~(CFG_PCIE_MEMSIZE - 1) | 3); break; case 2: mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE + port * CFG_PCIE_MEMSIZE)); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), ~(CFG_PCIE_MEMSIZE - 1) | 3); break; } /* Set up 16GB inbound memory window at 0 */ out_le32(mbase + PCI_BASE_ADDRESS_0, 0); out_le32(mbase + PCI_BASE_ADDRESS_1, 0); out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc); out_le32(mbase + PECFG_BAR0LMPA, 0); out_le32(mbase + PECFG_PIM0LAL, 0x00000000); out_le32(mbase + PECFG_PIM0LAH, 0x00000004); /* pointing to SRAM */ out_le32(mbase + PECFG_PIMEN, 0x1); /* Enable I/O, Mem, and Busmaster cycles */ out_le16((u16 *)(mbase + PCI_COMMAND), in_le16((u16 *)(mbase + PCI_COMMAND)) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */ out_le16(mbase + 0x202,0xfeed); /* Setting device ID */ attempts = 10; switch (port) { case 0: while (!(SDR_READ(PESDR0_RCSSTS) & (1 << 8))) { if (!(attempts--)) { printf("PCIE0: BMEN is not active\n"); return -1; } mdelay(1000); } break; case 1: while (!(SDR_READ(PESDR1_RCSSTS) & (1 << 8))) { if (!(attempts--)) { printf("PCIE1: BMEN is not active\n"); return -1; } mdelay(1000); } break; case 2: while (!(SDR_READ(PESDR2_RCSSTS) & (1 << 8))) { if (!(attempts--)) { printf("PCIE2: BMEN is not active\n"); return -1; } mdelay(1000); } break; } printf("PCIE:%d successfully set as endpoint\n",port); return 0; }
void ppc440spe_setup_pcie(struct pci_controller *hose, int port) { void __iomem *mbase; /* * Map 16MB, which is enough for 4 bits of bus # */ hose->cfg_data = ioremap64(0xc40000000ull + port * 0x40000000, 1 << 24); hose->ops = &pcie_pci_ops; /* * Set bus numbers on our root port */ mbase = ioremap64(0xc50000000ull + port * 0x40000000, 4096); out_8(mbase + PCI_PRIMARY_BUS, 0); out_8(mbase + PCI_SECONDARY_BUS, 0); /* * Set up outbound translation to hose->mem_space from PLB * addresses at an offset of 0xd_0000_0000. We set the low * bits of the mask to 11 to turn off splitting into 8 * subregions and to enable the outbound translation. */ out_le32(mbase + PECFG_POM0LAH, 0); out_le32(mbase + PECFG_POM0LAL, hose->mem_space.start); switch (port) { case 0: mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), hose->mem_space.start); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), ~(hose->mem_space.end - hose->mem_space.start) | 3); break; case 1: mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), hose->mem_space.start); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), ~(hose->mem_space.end - hose->mem_space.start) | 3); break; case 2: mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), hose->mem_space.start); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), ~(hose->mem_space.end - hose->mem_space.start) | 3); break; } /* Set up 16GB inbound memory window at 0 */ out_le32(mbase + PCI_BASE_ADDRESS_0, 0); out_le32(mbase + PCI_BASE_ADDRESS_1, 0); out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc); out_le32(mbase + PECFG_BAR0LMPA, 0); out_le32(mbase + PECFG_PIM0LAL, 0); out_le32(mbase + PECFG_PIM0LAH, 0); out_le32(mbase + PECFG_PIMEN, 0x1); /* Enable I/O, Mem, and Busmaster cycles */ out_le16(mbase + PCI_COMMAND, in_le16(mbase + PCI_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); iounmap(mbase); }
void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port) { volatile void *mbase = NULL; volatile void *rmbase = NULL; pci_set_ops(hose, pcie_read_config_byte, pcie_read_config_word, pcie_read_config_dword, pcie_write_config_byte, pcie_write_config_word, pcie_write_config_dword); switch (port) { case 0: mbase = (u32 *)CFG_PCIE0_XCFGBASE; rmbase = (u32 *)CFG_PCIE0_CFGBASE; hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE; break; case 1: mbase = (u32 *)CFG_PCIE1_XCFGBASE; rmbase = (u32 *)CFG_PCIE1_CFGBASE; hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE; break; case 2: mbase = (u32 *)CFG_PCIE2_XCFGBASE; rmbase = (u32 *)CFG_PCIE2_CFGBASE; hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE; break; } /* * Set bus numbers on our root port */ out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); /* * Set up outbound translation to hose->mem_space from PLB * addresses at an offset of 0xd_0000_0000. We set the low * bits of the mask to 11 to turn off splitting into 8 * subregions and to enable the outbound translation. */ out_le32(mbase + PECFG_POM0LAH, 0x00000000); out_le32(mbase + PECFG_POM0LAL, 0x00000000); switch (port) { case 0: mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + port * CFG_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), ~(CFG_PCIE_MEMSIZE - 1) | 3); break; case 1: mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE + port * CFG_PCIE_MEMSIZE)); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), ~(CFG_PCIE_MEMSIZE - 1) | 3); break; case 2: mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE + port * CFG_PCIE_MEMSIZE)); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), ~(CFG_PCIE_MEMSIZE - 1) | 3); break; } /* Set up 16GB inbound memory window at 0 */ out_le32(mbase + PCI_BASE_ADDRESS_0, 0); out_le32(mbase + PCI_BASE_ADDRESS_1, 0); out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc); out_le32(mbase + PECFG_BAR0LMPA, 0); out_le32(mbase + PECFG_PIM01SAH, 0xffff0000); out_le32(mbase + PECFG_PIM01SAL, 0x00000000); out_le32(mbase + PECFG_PIM0LAL, 0); out_le32(mbase + PECFG_PIM0LAH, 0); out_le32(mbase + PECFG_PIM1LAL, 0x00000000); out_le32(mbase + PECFG_PIM1LAH, 0x00000004); out_le32(mbase + PECFG_PIMEN, 0x1); /* Enable I/O, Mem, and Busmaster cycles */ out_le16((u16 *)(mbase + PCI_COMMAND), in_le16((u16 *)(mbase + PCI_COMMAND)) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); printf("PCIE:%d successfully set as rootpoint\n",port); }