static void __init ppc4xx_pic_impl_init(void) { /* Configure Base UIC */ mtdcr(DCRN_UIC_CR(UICB), 0); mtdcr(DCRN_UIC_TR(UICB), 0); mtdcr(DCRN_UIC_PR(UICB), 0xffffffff); mtdcr(DCRN_UIC_SR(UICB), 0xffffffff); mtdcr(DCRN_UIC_ER(UICB), UICB_UIC0NC | UICB_UIC1NC | UICB_UIC2NC); }
static void __init ppc4xx_pic_impl_init(void) { #if defined(CONFIG_440GX) /* Disable 440GP compatibility mode if it was enabled in firmware */ SDR_WRITE(DCRN_SDR_MFR, SDR_READ(DCRN_SDR_MFR) & ~DCRN_SDR_MFR_PCM); #endif /* Configure Base UIC */ mtdcr(DCRN_UIC_CR(UICB), 0); mtdcr(DCRN_UIC_TR(UICB), 0); mtdcr(DCRN_UIC_PR(UICB), 0xffffffff); mtdcr(DCRN_UIC_SR(UICB), 0xffffffff); mtdcr(DCRN_UIC_ER(UICB), UICB_UIC0NC | UICB_UIC1NC | UICB_UIC2NC); }
void __init ppc4xx_extpic_init(void) { /* set polarity * 1 = default/pos/rising , 0= neg/falling internal * 1 = neg/falling , 0= pos/rising external * Sense * 0 = default level internal * 0 = level, 1 = edge external */ unsigned int sense, irq; int bit, word; unsigned long ppc_cached_sense_mask[NR_MASK_WORDS]; unsigned long ppc_cached_pol_mask[NR_MASK_WORDS]; ppc_cached_sense_mask[0] = 0; ppc_cached_sense_mask[1] = 0; ppc_cached_pol_mask[0] = 0; ppc_cached_pol_mask[1] = 0; for (irq = 0; irq < NR_IRQS; irq++) { bit = irq & 0x1f; word = irq >> 5; sense = (irq < ibm4xxPIC_NumInitSenses) ? ibm4xxPIC_InitSenses[irq] : 3; #ifdef PPC4xx_PIC_DEBUG printk("PPC4xx_picext %d word:%x bit:%x sense:%x", irq, word, bit, sense); #endif ppc_cached_sense_mask[word] |= (sense & IRQ_SENSE_MASK) << (31 - bit); ppc_cached_pol_mask[word] |= ((sense & IRQ_POLARITY_MASK) >> 1) << (31 - bit); switch (word) { case 0: #ifdef PPC4xx_PIC_DEBUG printk("Pol %x ", mfdcr(DCRN_UIC_PR(UIC0))); printk("Level %x\n", mfdcr(DCRN_UIC_TR(UIC0))); #endif /* polarity setting */ mtdcr(DCRN_UIC_PR(UIC0), ppc_cached_pol_mask[word]); /* Level setting */ mtdcr(DCRN_UIC_TR(UIC0), ppc_cached_sense_mask[word]); break; case 1: #ifdef PPC4xx_PIC_DEBUG printk("Pol %x ", mfdcr(DCRN_UIC_PR(UIC1))); printk("Level %x\n", mfdcr(DCRN_UIC_TR(UIC1))); #endif /* polarity setting */ mtdcr(DCRN_UIC_PR(UIC1), ppc_cached_pol_mask[word]); /* Level setting */ mtdcr(DCRN_UIC_TR(UIC1), ppc_cached_sense_mask[word]); break; } } }