static void ddrmc_ctrl_lvl_init(struct ddrmc_lvl_info *lvl)
{
struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
u32 cr102 = 0, cr105 = 0, cr106 = 0, cr110 = 0;
if (lvl->wrlvl_reg_en) {
writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]);
writel(DDRMC_CR98_WRLVL_DL_0(lvl->wrlvl_dl_0), &ddrmr->cr[98]);
writel(DDRMC_CR99_WRLVL_DL_1(lvl->wrlvl_dl_1), &ddrmr->cr[99]);
}
if (lvl->rdlvl_reg_en) {
cr102 |= DDRMC_CR102_RDLVL_REG_EN;
cr105 |= DDRMC_CR105_RDLVL_DL_0(lvl->rdlvl_dl_0);
cr110 |= DDRMC_CR110_RDLVL_DL_1(lvl->rdlvl_dl_1);
}
if (lvl->rdlvl_gt_reg_en) {
cr102 |= DDRMC_CR102_RDLVL_GT_REGEN;
cr106 |= DDRMC_CR106_RDLVL_GTDL_0(lvl->rdlvl_gt_dl_0);
cr110 |= DDRMC_CR110_RDLVL_GTDL_1(lvl->rdlvl_gt_dl_1);
}
writel(cr102, &ddrmr->cr[102]);
writel(cr105, &ddrmr->cr[105]);
writel(cr106, &ddrmr->cr[106]);
writel(cr110, &ddrmr->cr[110]);
}
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
static struct ddrmc_cr_setting vf610twr_cr_settings[] = {
/* levelling */
{ DDRMC_CR97_WRLVL_EN, 97 },
{ DDRMC_CR98_WRLVL_DL_0(0), 98 },
{ DDRMC_CR99_WRLVL_DL_1(0), 99 },
{ DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 },
{ DDRMC_CR105_RDLVL_DL_0(0), 105 },
{ DDRMC_CR106_RDLVL_GTDL_0(4), 106 },
{ DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 },
/* AXI */
{ DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
{ DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
{ DDRMC_CR120_AXI0_PRI1_RPRI(2) |
DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
{ DDRMC_CR121_AXI0_PRI3_RPRI(2) |
DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
{ DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
DDRMC_CR122_AXI0_PRIRLX(100), 122 },
{ DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
