/** e1000_read_invm_word_i210 - Reads OTP
* @hw: pointer to the HW structure
* @address: the word address (aka eeprom offset) to read
* @data: pointer to the data read
*
* Reads 16-bit words from the OTP. Return error when the word is not
* stored in OTP.
**/
static s32 e1000_read_invm_word_i210(struct e1000_hw *hw, u8 address, u16 *data)
{
s32 status = -E1000_ERR_INVM_VALUE_NOT_FOUND;
u32 invm_dword;
u16 i;
u8 record_type, word_address;
DEBUGFUNC("e1000_read_invm_word_i210");
for (i = 0; i < E1000_INVM_SIZE; i++) {
invm_dword = E1000_READ_REG(hw, E1000_INVM_DATA_REG(i));
/* Get record type */
record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword);
if (record_type == E1000_INVM_UNINITIALIZED_STRUCTURE)
break;
if (record_type == E1000_INVM_CSR_AUTOLOAD_STRUCTURE)
i += E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS;
if (record_type == E1000_INVM_RSA_KEY_SHA256_STRUCTURE)
i += E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS;
if (record_type == E1000_INVM_WORD_AUTOLOAD_STRUCTURE) {
word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword);
if (word_address == address) {
*data = INVM_DWORD_TO_WORD_DATA(invm_dword);
DEBUGOUT2("Read INVM Word 0x%02x = %x",
address, *data);
status = E1000_SUCCESS;
break;
}
}
}
if (status != E1000_SUCCESS)
DEBUGOUT1("Requested word 0x%02x not found in OTP\n", address);
return status;
}
/**
* i40e_hmc_get_object_va - retrieves an object's virtual address
* @hw: pointer to the hw structure
* @object_base: pointer to u64 to get the va
* @rsrc_type: the hmc resource type
* @obj_idx: hmc object index
*
* This function retrieves the object's virtual address from the object
* base pointer. This function is used for LAN Queue contexts.
**/
static
enum i40e_status_code i40e_hmc_get_object_va(struct i40e_hw *hw,
u8 **object_base,
enum i40e_hmc_lan_rsrc_type rsrc_type,
u32 obj_idx)
{
u32 obj_offset_in_sd, obj_offset_in_pd;
struct i40e_hmc_info *hmc_info = &hw->hmc;
struct i40e_hmc_sd_entry *sd_entry;
struct i40e_hmc_pd_entry *pd_entry;
u32 pd_idx, pd_lmt, rel_pd_idx;
enum i40e_status_code ret_code = I40E_SUCCESS;
u64 obj_offset_in_fpm;
u32 sd_idx, sd_lmt;
if (NULL == hmc_info->hmc_obj) {
ret_code = I40E_ERR_BAD_PTR;
DEBUGOUT("i40e_hmc_get_object_va: bad hmc_info->hmc_obj ptr\n");
goto exit;
}
if (NULL == object_base) {
ret_code = I40E_ERR_BAD_PTR;
DEBUGOUT("i40e_hmc_get_object_va: bad object_base ptr\n");
goto exit;
}
if (I40E_HMC_INFO_SIGNATURE != hmc_info->signature) {
ret_code = I40E_ERR_BAD_PTR;
DEBUGOUT("i40e_hmc_get_object_va: bad hmc_info->signature\n");
goto exit;
}
if (obj_idx >= hmc_info->hmc_obj[rsrc_type].cnt) {
DEBUGOUT1("i40e_hmc_get_object_va: returns error %d\n",
ret_code);
ret_code = I40E_ERR_INVALID_HMC_OBJ_INDEX;
goto exit;
}
/* find sd index and limit */
I40E_FIND_SD_INDEX_LIMIT(hmc_info, rsrc_type, obj_idx, 1,
&sd_idx, &sd_lmt);
sd_entry = &hmc_info->sd_table.sd_entry[sd_idx];
obj_offset_in_fpm = hmc_info->hmc_obj[rsrc_type].base +
hmc_info->hmc_obj[rsrc_type].size * obj_idx;
if (I40E_SD_TYPE_PAGED == sd_entry->entry_type) {
I40E_FIND_PD_INDEX_LIMIT(hmc_info, rsrc_type, obj_idx, 1,
&pd_idx, &pd_lmt);
rel_pd_idx = pd_idx % I40E_HMC_PD_CNT_IN_SD;
pd_entry = &sd_entry->u.pd_table.pd_entry[rel_pd_idx];
obj_offset_in_pd = (u32)(obj_offset_in_fpm %
I40E_HMC_PAGED_BP_SIZE);
*object_base = (u8 *)pd_entry->bp.addr.va + obj_offset_in_pd;
} else {
obj_offset_in_sd = (u32)(obj_offset_in_fpm %
I40E_HMC_DIRECT_BP_SIZE);
*object_base = (u8 *)sd_entry->u.bp.addr.va + obj_offset_in_sd;
}
exit:
return ret_code;
}
/* Guckt ob Verbindung da und versucht aufzubauen.
* gibt 1 zurueck, wenn erfolgreich, sonst 0 */
static int pg_connect(){
if (PQstatus(connection) == CONNECTION_OK){
PQexec(connection,"SELECT 1"); /* Status neusetzen erzwingen */
}
if(PQstatus(connection) != CONNECTION_OK){
if (connection == NULL){
if(conn_string == NULL){
conn_string = malloc(sizeof(char)*512);
snprintf(conn_string, 512, "host=%s dbname=%s user=%s password=%s connect_timeout=%s", global_opts.pg_host, global_opts.pg_database, global_opts.pg_user, global_opts.pg_pass, global_opts.pg_timeout);
}
connection = PQconnectdb(conn_string); /* Connection aufbauen */
add_clean(clean_write, connection); /* Callbackfunktion zum Aufraeumen registrieren */
} else {
PQreset(connection); /* Connecion resetten */
}
if(PQstatus(connection) != CONNECTION_OK){
DEBUGOUT2("\nFehler beim Aufbau der Datenbankverbindung\n%s\n", PQerrorMessage(connection));
#ifndef NO_LOGING
snprintf(get_error_buffer(), ERR_BUFFERSIZE, "Fehler beim Aufbau der Datenbankverbindung: %s", PQerrorMessage(connection));
log_error(get_error_buffer());
#endif
return 0;
}
DEBUGOUT1("\nDatenbankverbindung erfolgreich hergestellt\n");
}
return 1;
}
HRESULT CNodeFactory::Error(IXMLNodeSource *pSource, HRESULT hrErrorCode,
USHORT cNumRecs, XML_NODE_INFO __RPC_FAR **aNodeInfo)
{
DEBUGOUT1(_pdbglog, 1, ID_FUSLOG_XML_PARSE_ERROR_CODE, hrErrorCode);
_nsmgr.Error(hrErrorCode);
return S_OK;
}
/* Bestimmung der Sensoren und Weiterreichung an die Funktionen zum auswerten der Werte
* sowie zum wegschreiben */
void process_data(time_t timestamp, u_char *buffer){
u_char type; /* Sensortyp */
u_char address; /* Sensoraddresse */
type = get_hi_nibble(remove_msb(buffer[1]));
address = get_lo_nibble(buffer[1]);
DEBUGOUT1(asctime(localtime(×tamp)));
switch (type){
case FERNB :
DEBUGOUT2("Fernbedienung an Addresse %i\n", address);
DEBUGOUT1("\nnoch nix zu implementiert!\n\n");
break;
case AUSS1 :
write_auss1(process_auss1(timestamp,address, buffer));
break;
case AUSS2 :
write_auss2(process_auss2(timestamp,address, buffer));
break;
case REGEN :
write_regen(process_regen(timestamp,address, buffer));
break;
case WINDS :
write_winds(process_winds(timestamp,address, buffer));
break;
case INNEN :
write_innen(process_innen(timestamp,address, buffer));
break;
case HELLI :
write_helli(process_helli(timestamp,address, buffer));
break;
case PYANO :
write_pyano(process_pyano(timestamp,address, buffer));
break;
}
}
/**
* e1000_setup_link_82542 - Setup flow control and link settings
* @hw: pointer to the HW structure
*
* Determines which flow control settings to use, then configures flow
* control. Calls the appropriate media-specific link configuration
* function. Assuming the adapter has a valid link partner, a valid link
* should be established. Assumes the hardware has previously been reset
* and the transmitter and receiver are not enabled.
**/
static s32 e1000_setup_link_82542(struct e1000_hw *hw)
{
struct e1000_mac_info *mac = &hw->mac;
s32 ret_val = E1000_SUCCESS;
DEBUGFUNC("e1000_setup_link_82542");
ret_val = e1000_set_default_fc_generic(hw);
if (ret_val)
goto out;
hw->fc.requested_mode &= ~e1000_fc_tx_pause;
if (mac->report_tx_early == 1)
hw->fc.requested_mode &= ~e1000_fc_rx_pause;
/*
* Save off the requested flow control mode for use later. Depending
* on the link partner's capabilities, we may or may not use this mode.
*/
hw->fc.current_mode = hw->fc.requested_mode;
DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
hw->fc.current_mode);
/* Call the necessary subroutine to configure the link. */
ret_val = mac->ops.setup_physical_interface(hw);
if (ret_val)
goto out;
/*
* Initialize the flow control address, type, and PAUSE timer
* registers to their default values. This is done even if flow
* control is disabled, because it does not hurt anything to
* initialize these registers.
*/
DEBUGOUT("Initializing Flow Control address, type and timer regs\n");
E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
ret_val = e1000_set_fc_watermarks_generic(hw);
out:
return ret_val;
}
/**
* e1000_setup_link_82542 - Setup flow control and link settings
* @hw: pointer to the HW structure
*
* Determines which flow control settings to use, then configures flow
* control. Calls the appropriate media-specific link configuration
* function. Assuming the adapter has a valid link partner, a valid link
* should be established. Assumes the hardware has previously been reset
* and the transmitter and receiver are not enabled. This is a function
* pointer entry point called by the api module.
**/
static s32 e1000_setup_link_82542(struct e1000_hw *hw)
{
struct e1000_mac_info *mac = &hw->mac;
s32 ret_val = E1000_SUCCESS;
DEBUGFUNC("e1000_setup_link_82542");
ret_val = e1000_set_default_fc_generic(hw);
if (ret_val)
goto out;
hw->fc.type &= ~e1000_fc_tx_pause;
if (mac->report_tx_early == 1)
hw->fc.type &= ~e1000_fc_rx_pause;
/*
* We want to save off the original Flow Control configuration just in
* case we get disconnected and then reconnected into a different hub
* or switch with different Flow Control capabilities.
*/
hw->fc.original_type = hw->fc.type;
DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc.type);
/* Call the necessary subroutine to configure the link. */
ret_val = mac->ops.setup_physical_interface(hw);
if (ret_val)
goto out;
/*
* Initialize the flow control address, type, and PAUSE timer
* registers to their default values. This is done even if flow
* control is disabled, because it does not hurt anything to
* initialize these registers.
*/
DEBUGOUT("Initializing Flow Control address, type and timer regs\n");
E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
ret_val = e1000_set_fc_watermarks_generic(hw);
out:
return ret_val;
}
/**
* e1000_read_phy_reg_82543 - Read PHY register
* @hw: pointer to the HW structure
* @offset: register offset to be read
* @data: pointer to the read data
*
* Reads the PHY at offset and stores the information read to data.
**/
static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data)
{
u32 mdic;
s32 ret_val = E1000_SUCCESS;
DEBUGFUNC("e1000_read_phy_reg_82543");
if (offset > MAX_PHY_REG_ADDRESS) {
DEBUGOUT1("PHY Address %d is out of range\n", offset);
ret_val = -E1000_ERR_PARAM;
goto out;
}
/*
* We must first send a preamble through the MDIO pin to signal the
* beginning of an MII instruction. This is done by sending 32
* consecutive "1" bits.
*/
e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
/*
* Now combine the next few fields that are required for a read
* operation. We use this method instead of calling the
* e1000_shift_out_mdi_bits routine five different times. The format
* of an MII read instruction consists of a shift out of 14 bits and
* is defined as follows:
* <Preamble><SOF><Op Code><Phy Addr><Offset>
* followed by a shift in of 18 bits. This first two bits shifted in
* are TurnAround bits used to avoid contention on the MDIO pin when a
* READ operation is performed. These two bits are thrown away
* followed by a shift in of 16 bits which contains the desired data.
*/
mdic = (offset | (hw->phy.addr << 5) |
(PHY_OP_READ << 10) | (PHY_SOF << 12));
e1000_shift_out_mdi_bits_82543(hw, mdic, 14);
/*
* Now that we've shifted out the read command to the MII, we need to
* "shift in" the 16-bit value (18 total bits) of the requested PHY
* register address.
*/
*data = e1000_shift_in_mdi_bits_82543(hw);
out:
return ret_val;
}
/**
* e1000_read_nvm_i211 - Read NVM wrapper function for I211
* @hw: pointer to the HW structure
* @address: the word address (aka eeprom offset) to read
* @data: pointer to the data read
*
* Wrapper function to return data formerly found in the NVM.
**/
static s32 e1000_read_nvm_i211(struct e1000_hw *hw, u16 offset, u16 words,
u16 *data)
{
s32 ret_val = E1000_SUCCESS;
DEBUGFUNC("e1000_read_nvm_i211");
/* Only the MAC addr is required to be present in the iNVM */
switch (offset) {
case NVM_MAC_ADDR:
ret_val = e1000_read_invm_i211(hw, (u8)offset, &data[0]);
ret_val |= e1000_read_invm_i211(hw, (u8)offset+1, &data[1]);
ret_val |= e1000_read_invm_i211(hw, (u8)offset+2, &data[2]);
if (ret_val != E1000_SUCCESS)
DEBUGOUT("MAC Addr not found in iNVM\n");
break;
case NVM_ID_LED_SETTINGS:
case NVM_INIT_CTRL_2:
case NVM_INIT_CTRL_4:
case NVM_LED_1_CFG:
case NVM_LED_0_2_CFG:
e1000_read_invm_i211(hw, (u8)offset, data);
break;
case NVM_COMPAT:
*data = ID_LED_DEFAULT_I210;
break;
case NVM_SUB_DEV_ID:
*data = hw->subsystem_device_id;
break;
case NVM_SUB_VEN_ID:
*data = hw->subsystem_vendor_id;
break;
case NVM_DEV_ID:
*data = hw->device_id;
break;
case NVM_VEN_ID:
*data = hw->vendor_id;
break;
default:
DEBUGOUT1("NVM word 0x%02x is not mapped.\n", offset);
*data = NVM_RESERVED_WORD;
break;
}
return ret_val;
}
HRESULT CNodeFactory::QualifyAssembly(LPCWSTR pwzDisplayName, IAssemblyName **ppNameQualified, CDebugLog *pdbglog)
{
HRESULT hr = S_OK;
LPWSTR wzDispName=NULL;
DWORD dwSize;
CQualifyAssembly *pqa;
LISTNODE pos;
wzDispName = NEW(WCHAR[MAX_URL_LENGTH+1]);
if (!wzDispName)
{
hr = E_OUTOFMEMORY;
goto Exit;
}
pos = _listQualifyAssembly.GetHeadPosition();
while (pos) {
pqa = _listQualifyAssembly.GetNext(pos);
if (!lstrcmpW(pwzDisplayName, pqa->_pwzPartialName)) {
// Found match
*ppNameQualified = pqa->_pNameFull;
(*ppNameQualified)->AddRef();
dwSize = MAX_URL_LENGTH;
if ((*ppNameQualified)->GetDisplayName(wzDispName, &dwSize, 0) == S_OK) {
DEBUGOUT1(pdbglog, 0, ID_FUSLOG_QUALIFIED_ASSEMBLY, wzDispName);
}
goto Exit;
}
}
// No match found
hr = HRESULT_FROM_WIN32(ERROR_NOT_FOUND);
Exit:
SAFEDELETEARRAY(wzDispName);
return hr;
}
/* Wertkonvertierungen fuer den Regensensor (ein Zaehlschritt = 370ml/m^2)*/
static regen_data process_regen(time_t timestamp, u_char address, u_char *buffer){
regen_data data; /* Datenstruktur */
int new_rain_count = 0; /* Neuer Zaehlerstand */
int now_rain_count = 0; /* Delta-Zaehlerstand */
data.timestamp = timestamp; /* Zeitstempel */
data.address = address; /* Addresse */
new_rain_count = ((buffer[2] & 0x1F) << 7) | remove_msb(buffer[3]); /* Niederschlagszaehler */
if (get_flag(NOT_USE_ADDR_FLAG))
address = 0;
if(last_rain_count[address%16] == -1) /* Nach Programmstart Zaehler initialisieren */
last_rain_count[address%16] = new_rain_count;
now_rain_count = new_rain_count - last_rain_count[address%16]; /* neuen Niederschlag berechnen */
if(now_rain_count < 0){ /* Wenn Integerueberlauf im Sensor */
now_rain_count = (0x3FFF - last_rain_count[address%16]) + new_rain_count; /* Dann letzten gemessenen Wert vom Max-Integer-Wert abziehen und neuen Zaehlwert dazurechnen */
DEBUGOUT1("Integer-Ueberlauf\n");
}
data.counter = (now_rain_count * 370); /* Ein Zaehlschritt entspricht 370ml/m^2, also aenderung mit 370 multiplizieren und zuweisen */
last_rain_count[address%16] = new_rain_count; /* Zaehler neu setzen */
DEBUGOUT2("Regensensor an Addresse %i\n", data.address);
DEBUGOUT3("Zaehler: %d Differenz: %d\n", new_rain_count,now_rain_count);
DEBUGOUT2("Niederschlag: %dml/m^2\n", data.counter);
#ifndef NO_LOGING
if(get_flag(LOG_DATA_FLAG)){
check_log_buffer();
sprintf(prepend_type_address(REGEN,address), "Rain: %dml/m^2",data.counter);
log_data(timestamp, log_buffer);
}
#endif
return data;
}
/**
* e1000_write_phy_reg_82543 - Write PHY register
* @hw: pointer to the HW structure
* @offset: register offset to be written
* @data: pointer to the data to be written at offset
*
* Writes data to the PHY at offset.
**/
static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data)
{
u32 mdic;
s32 ret_val = E1000_SUCCESS;
DEBUGFUNC("e1000_write_phy_reg_82543");
if (offset > MAX_PHY_REG_ADDRESS) {
DEBUGOUT1("PHY Address %d is out of range\n", offset);
ret_val = -E1000_ERR_PARAM;
goto out;
}
/*
* We'll need to use the SW defined pins to shift the write command
* out to the PHY. We first send a preamble to the PHY to signal the
* beginning of the MII instruction. This is done by sending 32
* consecutive "1" bits.
*/
e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
/*
* Now combine the remaining required fields that will indicate a
* write operation. We use this method instead of calling the
* e1000_shift_out_mdi_bits routine for each field in the command. The
* format of a MII write instruction is as follows:
* <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
*/
mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) |
(PHY_OP_WRITE << 12) | (PHY_SOF << 14));
mdic <<= 16;
mdic |= (u32) data;
e1000_shift_out_mdi_bits_82543(hw, mdic, 32);
out:
return ret_val;
}
/**
* at_intr - Interrupt Handler
* @irq: interrupt number
* @data: pointer to a network interface device structure
* @pt_regs: CPU registers structure
**/
void AttansicL2Ethernet::atIntr(OSObject *client, IOInterruptEventSource *src, int count)
{
at_adapter *adapter = &adapter_;
at_hw *hw = &adapter->hw;
u32 status;
status = AT_READ_REG(hw, REG_ISR);
if (0 == status)
return ;
// link event
if (status&ISR_PHY) {
at_clear_phy_int(adapter);
}
// clear ISR status, and Enable CMB DMA/Disable Interrupt
AT_WRITE_REG(hw, REG_ISR, status|ISR_DIS_INT);
// check if PCIE PHY Link down
if (status&ISR_PHY_LINKDOWN) {
DEBUGOUT1("pcie phy linkdown %x\n", status);
// reset MAC
AT_WRITE_REG(hw, REG_ISR, 0);
AT_WRITE_REG(hw, REG_IMR, 0);
AT_WRITE_FLUSH(hw);
at_reset_hw(adapter);
return ;
}
// check if DMA read/write error ?
if (status&(ISR_DMAR_TO_RST|ISR_DMAW_TO_RST))
{
DEBUGOUT1("PCIE DMA RW error (status = 0x%x) !\n", status);
//AT_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
AT_WRITE_REG(hw, REG_ISR, 0);
AT_WRITE_REG(hw, REG_IMR, 0);
AT_WRITE_FLUSH(hw);
at_reset_hw(adapter);
return ;
}
// link event
if (status&(ISR_PHY|ISR_MANUAL))
{
IOSleep(2);
atGetAndUpdateLinkStatus();
}
// transmit event
if ( status&ISR_TX_EVENT ) {
at_intr_tx(adapter);
}
// rx exception
if ( status& ISR_RX_EVENT ) {
at_intr_rx(adapter);
}
// re-enable Interrupt
AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
}
HRESULT CAssemblyDownload::KickOffDownload(BOOL bFirstDownload)
{
HRESULT hr = S_OK;
LPWSTR pwzUrl = NULL;
WCHAR wzFilePath[MAX_PATH];
BOOL bIsFileUrl = FALSE;
CCriticalSection cs(&_cs);
CCriticalSection csDownload(&g_csDownload);
wzFilePath[0] = L'\0';
// If we're aborted, or done, we can't do anything here
hr = cs.Lock();
if (FAILED(hr)) {
goto Exit;
}
if (_state == ADLSTATE_DONE) {
hr = S_FALSE;
goto Exit;
}
// Dupe detection. If we end up hitting a dupe, then the CClientBinding
// that was keeping a refcount on us, releases us, and adds itself as
// a client to the duped download. In this case, we'll come back, and
// this download object could be destroyed--that's why we AddRef/Release
// around the dupe checking code.
if (bFirstDownload) {
// This is a top-level download (ie. not a probe download called from
// DownloadNextCodebase
AddRef();
hr = CheckDuplicate();
if (hr == E_PENDING) {
cs.Unlock();
Release();
goto Exit;
}
Release();
// Not a duplicate. Add ourselves to the global download list.
hr = csDownload.Lock();
if (FAILED(hr)) {
goto Exit;
}
AddRef();
g_pDownloadList->AddTail(this);
csDownload.Unlock();
}
// Careful! PrepNextDownload/CompleteAll call the client back!
cs.Unlock();
hr = GetNextCodebase(&bIsFileUrl, wzFilePath, MAX_PATH);
if (hr == HRESULT_FROM_WIN32(ERROR_NO_MORE_ITEMS)) {
// This must have been a case where all remaining probing URLs were file://,
// and none of them existed. That is, we never get here (KickOffDownload)
// unless the codebase list is non-empty, so this return result
// from GetNextCodebase could only have resulted because we rejected
// all remaining URLs.
hr = DownloadComplete(HRESULT_FROM_WIN32(ERROR_FILE_NOT_FOUND), NULL, NULL, FALSE);
// Not really pending, just tell client the result is reported via
// bind sink.
if (SUCCEEDED(hr)) {
hr = E_PENDING;
}
goto Exit;
}
else if (FAILED(hr)) {
DEBUGOUT1(_pdbglog, 1, ID_FUSLOG_CODEBASE_RETRIEVE_FAILURE, hr);
goto Exit;
}
DEBUGOUT1(_pdbglog, 0, ID_FUSLOG_ATTEMPT_NEW_DOWNLOAD, _pwzUrl);
if (bIsFileUrl) {
hr = DownloadComplete(S_OK, wzFilePath, NULL, FALSE);
// We're not really pending, but E_PENDING means that the client
// will get the IAssembly via the bind sink (not the ppv returned
// in the call to BindToObject).
if (SUCCEEDED(hr)) {
hr = E_PENDING;
}
goto Exit;
}
else {
hr = HRESULT_FROM_WIN32(ERROR_NOT_SUPPORTED);
goto Exit;
}
Exit:
SAFEDELETEARRAY(pwzUrl);
if (FAILED(hr) && hr != E_PENDING) {
LISTNODE listnode;
CCriticalSection cs(&g_csDownload);
// Fatal error!
// If we added ourselves to the download list, we should remove
// ourselves immediately!
HRESULT hrLock = cs.Lock();
if (FAILED(hrLock)) {
return hrLock;
}
listnode = g_pDownloadList->Find(this);
if (listnode) {
g_pDownloadList->RemoveAt(listnode);
// release ourselves since we are removing from the global dl list
Release();
}
cs.Unlock();
}
return hr;
}
void AtherosL1Ethernet::at_clean_rx_irq(at_adapter *adapter)
{
mbuf_t skb = NULL;
u32 packet_size;
int i, count;
u16 length, rrd_next_to_clean;
struct at_rfd_ring *rfd_ring = &adapter->rfd_ring;
struct at_rrd_ring *rrd_ring = &adapter->rrd_ring;
struct at_buffer * buffer_info;
rx_return_desc_t* rrd;
count = 0;
rrd_next_to_clean = (u16)atomic_read(&rrd_ring->next_to_clean);
DEBUGOUT1("at_clean_rx_irq() rrd_next_to_clean=%d\n",
rrd_next_to_clean);
while (1)
{
rrd = AT_RRD_DESC(rrd_ring, rrd_next_to_clean);
i = 1;
if (rrd->xsz.valid) { // packet valid
chk_rrd:
// check rrd status
if (rrd->num_buf != 1) {
DEBUGOUT1("RRD NumRfd %d\n", rrd->num_buf);
DEBUGOUT1("packet length = %d\n", rrd->xsz.xsum_sz.pkt_size);
} else {
goto rrd_ok;
}
// rrd seems to be bad
if (i-- > 0) { // rrd may not be DMAed completely
DEBUGOUT("RRD may not be DMAed completely\n");
usec_delay(1);
goto chk_rrd;
}
// bad rrd
AT_ERR("BAD RRD\n");
// see if update RFD index
if (rrd->num_buf > 1) {
u16 num_buf;
num_buf =
(rrd->xsz.xsum_sz.pkt_size+adapter->rx_buffer_len - 1)/
adapter->rx_buffer_len;
DEBUGOUT1("RRD.buf_index (%d)\n", rrd->buf_indx);
if (rrd->num_buf == num_buf) {
// clean alloc flag for bad rrd
while (rfd_ring->next_to_clean !=
(rrd->buf_indx + num_buf) ) {
DEBUGOUT1("clear index (%d)\n", rfd_ring->next_to_clean);
rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced = 0;
if (++rfd_ring->next_to_clean == rfd_ring->count) {
rfd_ring->next_to_clean = 0;
}
} // end while
} // end if (rrd->num_buf == ...)
}
// update rrd
rrd->xsz.valid = 0;
if (++rrd_next_to_clean == rrd_ring->count)
rrd_next_to_clean = 0;
count++;
continue;
} else { // current rrd still not be updated
break;
}
rrd_ok:
// clean alloc flag for bad rrd
while (rfd_ring->next_to_clean != rrd->buf_indx) {
rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced = 0;
if (++rfd_ring->next_to_clean == rfd_ring->count) {
rfd_ring->next_to_clean = 0;
}
}
buffer_info = &rfd_ring->buffer_info[rrd->buf_indx];
if (++rfd_ring->next_to_clean == rfd_ring->count) {
rfd_ring->next_to_clean = 0;
}
// update rrd next to clean
if (++rrd_next_to_clean == rrd_ring->count)
rrd_next_to_clean = 0;
count++;
if (rrd->pkt_flg&PACKET_FLAG_ERR) {
if (rrd->err_flg&
(ERR_FLAG_CRC|ERR_FLAG_TRUNC|ERR_FLAG_CODE|ERR_FLAG_OV)) {
/* packet error , don't need upstream */
buffer_info->alloced = 0;
rrd->xsz.valid = 0;
DEBUGOUT1("rrd error flag %x\n", rrd->err_flg);
continue;
}
}
/* Good Receive */
length = OSSwapLittleToHostInt16(rrd->xsz.xsum_sz.pkt_size);
packet_size = length - 4; // CRC
// alloc new buffer
skb = allocatePacket(packet_size + 2);
if (NULL == skb) {
DbgPrint("Memory squeeze, deferring packet.\n");
break;
}
DEBUGOUT1("pktsize=%d\n", packet_size);
// copy packet to user buffer
if (buffer_info->memDesc)
{
memcpy( mbuf_data(skb),buffer_info->memDesc->getBytesNoCopy(), packet_size);
}
//TO-DO: Add network stack notification
netIface_->inputPacket(skb, packet_size, IONetworkInterface::kInputOptionQueuePacket);
netIface_->flushInputQueue();
/*
DEBUGOUT1("pkt:%02x %02x %02x %02x %02x %02x-%02x\n",
skb->data[0], skb->data[1], skb->data[2],
skb->data[3], skb->data[4], skb->data[5],
skb->data[12]);
*/
// let protocol layer free skb
buffer_info->alloced = 0;
rrd->xsz.valid = 0;
}
atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean);
at_alloc_rx_buffers(adapter);
// update mailbox ?
if (0 != count) {
at_update_mailbox(adapter);
}
}
/**
* at_intr - Interrupt Handler
**/
void AtherosL1Ethernet::atIntr(OSObject *client, IOInterruptEventSource *src, int count)
{
at_adapter *adapter = &adapter_;
at_hw *hw = &adapter->hw;
u32 status;
int max_ints = 12;
DEBUGFUNC("at_intr() !\n");
if (0 == (status = adapter->cmb.cmb->int_stats))
return ;
DEBUGOUT("atIntr() status = 0x%x!\n", status);
loopint:
// clear CMB interrupt status at once
adapter->cmb.cmb->int_stats = 0;
if (status & ISR_GPHY) { // clear phy status
at_clear_phy_int(adapter);
}
// Ack ISR
AT_WRITE_REG(hw, REG_ISR, (status|ISR_DIS_INT|ISR_DIS_DMA));
// check if PCIE PHY Link down
if (status&ISR_PHY_LINKDOWN) {
DEBUGOUT1("pcie phy linkdown %x\n", status);
AT_WRITE_REG(hw, REG_ISR, 0);
AT_WRITE_REG(hw, REG_IMR, 0);
AT_WRITE_FLUSH(hw);
at_reset_hw(hw);
return ;
}
// check if DMA read/write error ?
if (status&(ISR_DMAR_TO_RST|ISR_DMAW_TO_RST))
{
DEBUGOUT1("PCIE DMA RW error (status = 0x%x) !\n", status);
//AT_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
AT_WRITE_REG(hw, REG_ISR, 0);
AT_WRITE_REG(hw, REG_IMR, 0);
AT_WRITE_FLUSH(hw);
at_reset_hw(hw);
return ;
}
// check if SMB intr
if (status & ISR_SMB) {
at_inc_smb(adapter);
}
// link event
if (status&(ISR_GPHY|ISR_MANUAL))
{
IOSleep(2);
atGetAndUpdateLinkStatus();
}
// transmit event
if ( status & ISR_TX_EVENT ) {
at_clean_tx_irq(adapter);
}
// recv event
if ( status & ISR_RX_EVENT ) {
at_clean_rx_irq(adapter);
}
if (--max_ints > 0 &&
0 != (status = adapter->cmb.cmb->int_stats)) {
goto loopint;
}
// re-enable Interrupt
AT_WRITE_REG(&adapter->hw, REG_ISR, ISR_DIS_SMB|ISR_DIS_DMA);
}
/**
* ixgbe_setup_fiber_serdes_link_82598 - Configure fiber serdes link
* @hw: pointer to hardware structure
*
* Sets up PCS registers and sets flow control settings, based on
* link-partner's abilities.
**/
int32_t ixgbe_setup_fiber_serdes_link_82598(struct ixgbe_hw *hw)
{
uint32_t reg;
int32_t ret_val;
DEBUGFUNC("ixgbe_setup_fiber_serdes_link_82598");
/*
* 10 gig parts do not have a word in the EEPROM to determine the
* default flow control setting, so we explicitly set it to full.
*/
if (hw->fc.type == ixgbe_fc_default)
hw->fc.type = ixgbe_fc_full;
/*
* 82598 fiber/serdes devices require that flow control be resolved in
* software.
*/
reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
/*
* The possible values of the "fc" parameter are:
* 0: Flow control is completely disabled
* 1: Rx flow control is enabled (we can receive pause frames,
* but not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames but
* we do not support receiving pause frames).
* 3: Both Rx and Tx flow control (symmetric) are enabled.
*/
switch (hw->fc.type) {
case ixgbe_fc_none:
/*
* Flow control completely disabled by a software
* over-ride.
*/
reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
break;
case ixgbe_fc_rx_pause:
/*
* Rx Flow control is enabled and Tx Flow control is
* disabled by a software over-ride. Since there really
* isn't a way to advertise that we are capable of RX
* Pause ONLY, we will advertise that we support both
* symmetric and asymmetric Rx PAUSE. Later, we will
* disable the adapter's ability to send PAUSE frames.
*/
reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
break;
case ixgbe_fc_tx_pause:
/*
* Tx Flow control is enabled, and Rx Flow control is
* disabled, by a software over-ride.
*/
reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
break;
case ixgbe_fc_full:
/*
* Flow control (both Rx and Tx) is enabled by a
* software over-ride.
*/
reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
break;
default:
DEBUGOUT("Flow control param set incorrectly\n");
ret_val = -IXGBE_ERR_CONFIG;
goto out;
break;
}
IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
/* Set PCS register for autoneg */
/* Enable and restart autoneg */
reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART;
reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; /* Disable AN timeout */
DEBUGOUT1("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
/*
* Configure flow control. If we aren't auto-negotiating,
* just setup the flow control and do not worry about PCS autoneg.
*/
ixgbe_configure_fiber_serdes_fc_82598(hw);
out:
return IXGBE_SUCCESS;
}
/**
* i40e_configure_lan_hmc - prepare the HMC backing store
* @hw: pointer to the hw structure
* @model: the model for the layout of the SD/PD tables
*
* - This function will be called once per physical function initialization.
* - This function will be called after i40e_init_lan_hmc() and before
* any LAN/FCoE HMC objects can be created.
**/
enum i40e_status_code i40e_configure_lan_hmc(struct i40e_hw *hw,
enum i40e_hmc_model model)
{
struct i40e_hmc_lan_create_obj_info info;
u8 hmc_fn_id = hw->hmc.hmc_fn_id;
struct i40e_hmc_obj_info *obj;
enum i40e_status_code ret_code = I40E_SUCCESS;
/* Initialize part of the create object info struct */
info.hmc_info = &hw->hmc;
info.rsrc_type = I40E_HMC_LAN_FULL;
info.start_idx = 0;
info.direct_mode_sz = hw->hmc.hmc_obj[I40E_HMC_LAN_FULL].size;
/* Build the SD entry for the LAN objects */
switch (model) {
case I40E_HMC_MODEL_DIRECT_PREFERRED:
case I40E_HMC_MODEL_DIRECT_ONLY:
info.entry_type = I40E_SD_TYPE_DIRECT;
/* Make one big object, a single SD */
info.count = 1;
ret_code = i40e_create_lan_hmc_object(hw, &info);
if ((ret_code != I40E_SUCCESS) && (model == I40E_HMC_MODEL_DIRECT_PREFERRED))
goto try_type_paged;
else if (ret_code != I40E_SUCCESS)
goto configure_lan_hmc_out;
/* else clause falls through the break */
break;
case I40E_HMC_MODEL_PAGED_ONLY:
try_type_paged:
info.entry_type = I40E_SD_TYPE_PAGED;
/* Make one big object in the PD table */
info.count = 1;
ret_code = i40e_create_lan_hmc_object(hw, &info);
if (ret_code != I40E_SUCCESS)
goto configure_lan_hmc_out;
break;
default:
/* unsupported type */
ret_code = I40E_ERR_INVALID_SD_TYPE;
DEBUGOUT1("i40e_configure_lan_hmc: Unknown SD type: %d\n",
ret_code);
goto configure_lan_hmc_out;
}
/* Configure and program the FPM registers so objects can be created */
/* Tx contexts */
obj = &hw->hmc.hmc_obj[I40E_HMC_LAN_TX];
wr32(hw, I40E_GLHMC_LANTXBASE(hmc_fn_id),
(u32)((obj->base & I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK) / 512));
wr32(hw, I40E_GLHMC_LANTXCNT(hmc_fn_id), obj->cnt);
/* Rx contexts */
obj = &hw->hmc.hmc_obj[I40E_HMC_LAN_RX];
wr32(hw, I40E_GLHMC_LANRXBASE(hmc_fn_id),
(u32)((obj->base & I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK) / 512));
wr32(hw, I40E_GLHMC_LANRXCNT(hmc_fn_id), obj->cnt);
/* FCoE contexts */
obj = &hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX];
wr32(hw, I40E_GLHMC_FCOEDDPBASE(hmc_fn_id),
(u32)((obj->base & I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK) / 512));
wr32(hw, I40E_GLHMC_FCOEDDPCNT(hmc_fn_id), obj->cnt);
/* FCoE filters */
obj = &hw->hmc.hmc_obj[I40E_HMC_FCOE_FILT];
wr32(hw, I40E_GLHMC_FCOEFBASE(hmc_fn_id),
(u32)((obj->base & I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK) / 512));
wr32(hw, I40E_GLHMC_FCOEFCNT(hmc_fn_id), obj->cnt);
configure_lan_hmc_out:
return ret_code;
}
VOID CheckForLink(PADAPTER_STRUCT Adapter)
{
UINT32 RxcwRegValue;
UINT32 CtrlRegValue;
UINT32 StatusRegValue;
UINT16 PhyData;
DEBUGFUNC("CheckForLink")
CtrlRegValue = E1000_READ_REG(Ctrl);
StatusRegValue = E1000_READ_REG(Status);
RxcwRegValue = E1000_READ_REG(Rxcw);
if (Adapter->MediaType == MEDIA_TYPE_COPPER && Adapter->GetLinkStatus) {
PhyData = ReadPhyRegister(Adapter,
PHY_MII_STATUS_REG, Adapter->PhyAddress);
PhyData = ReadPhyRegister(Adapter,
PHY_MII_STATUS_REG, Adapter->PhyAddress);
if (PhyData & MII_SR_LINK_STATUS)
Adapter->GetLinkStatus = FALSE;
else {
DEBUGOUT("**** CFL - No link detected. ****\r\n");
return;
}
if (!Adapter->AutoNeg)
return;
switch (Adapter->PhyId) {
case PAXSON_PHY_88E1000:
case PAXSON_PHY_88E1000S:
PhyData = ReadPhyRegister(Adapter,
PXN_PHY_SPEC_STAT_REG,
Adapter->PhyAddress);
DEBUGOUT1("CFL - Auto-Neg complete. PhyData = %x\r\n",
PhyData);
ConfigureMacToPhySettings(Adapter, PhyData);
ConfigFlowControlAfterLinkUp(Adapter);
break;
default:
DEBUGOUT("CFL - Invalid PHY detected.\r\n");
}
}
else
if ((Adapter->MediaType == MEDIA_TYPE_FIBER) &&
(!(StatusRegValue & E1000_STATUS_LU)) &&
(!(CtrlRegValue & E1000_CTRL_SWDPIN1)) &&
(!(RxcwRegValue & E1000_RXCW_C))) {
if (Adapter->AutoNegFailed == 0) {
Adapter->AutoNegFailed = 1;
return;
}
DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
E1000_WRITE_REG(Txcw, (Adapter->TxcwRegValue & ~E1000_TXCW_ANE));
CtrlRegValue = E1000_READ_REG(Ctrl);
CtrlRegValue |= (E1000_CTRL_SLU | E1000_CTRL_FD);
E1000_WRITE_REG(Ctrl, CtrlRegValue);
ConfigFlowControlAfterLinkUp(Adapter);
}
else if ((Adapter->MediaType == MEDIA_TYPE_FIBER) &&
(CtrlRegValue & E1000_CTRL_SLU) &&
(RxcwRegValue & E1000_RXCW_C)) {
DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
E1000_WRITE_REG(Txcw, Adapter->TxcwRegValue);
E1000_WRITE_REG(Ctrl, (CtrlRegValue & ~E1000_CTRL_SLU));
}
return;
}
BOOLEAN SetupFlowControlAndLink(PADAPTER_STRUCT Adapter)
{
UINT32 TempEepromWord;
UINT32 DeviceControlReg;
UINT32 DeviceStatusReg;
UINT32 ExtDevControlReg;
BOOLEAN Status = TRUE;
DEBUGFUNC("SetupFlowControlAndLink")
TempEepromWord = ReadEepromWord(Adapter, EEPROM_INIT_CONTROL1_REG);
DeviceControlReg =
(((TempEepromWord & EEPROM_WORD0A_SWDPIO) << SWDPIO_SHIFT) |
((TempEepromWord & EEPROM_WORD0A_ILOS) << ILOS_SHIFT));
if (Adapter->DmaFairness)
DeviceControlReg |= E1000_CTRL_PRIOR;
TempEepromWord = ReadEepromWord(Adapter, EEPROM_INIT_CONTROL2_REG);
if (Adapter->FlowControl > FLOW_CONTROL_FULL) {
if ((TempEepromWord & EEPROM_WORD0F_PAUSE_MASK) == 0)
Adapter->FlowControl = FLOW_CONTROL_NONE;
else if ((TempEepromWord & EEPROM_WORD0F_PAUSE_MASK) ==
EEPROM_WORD0F_ASM_DIR) Adapter->FlowControl =
FLOW_CONTROL_TRANSMIT_PAUSE;
else
Adapter->FlowControl = FLOW_CONTROL_FULL;
}
Adapter->OriginalFlowControl = Adapter->FlowControl;
if (Adapter->MacType == MAC_WISEMAN_2_0)
Adapter->FlowControl &= (~FLOW_CONTROL_TRANSMIT_PAUSE);
if ((Adapter->MacType < MAC_LIVENGOOD)
&& (Adapter->ReportTxEarly == 1)) Adapter->FlowControl &=
(~FLOW_CONTROL_RECEIVE_PAUSE);
DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
Adapter->FlowControl);
if (Adapter->MacType >= MAC_LIVENGOOD) {
ExtDevControlReg = ((TempEepromWord & EEPROM_WORD0F_SWPDIO_EXT)
<< SWDPIO__EXT_SHIFT);
E1000_WRITE_REG(Exct, ExtDevControlReg);
}
if (Adapter->MacType >= MAC_LIVENGOOD) {
if (Adapter->MediaType == MEDIA_TYPE_FIBER) {
Status = SetupPcsLink(Adapter, DeviceControlReg);
}
else {
Status = PhySetup(Adapter, DeviceControlReg);
}
} else {
Status = SetupPcsLink(Adapter, DeviceControlReg);
}
DEBUGOUT
("Initializing the Flow Control address, type and timer regs\n");
E1000_WRITE_REG(Fcal, FLOW_CONTROL_ADDRESS_LOW);
E1000_WRITE_REG(Fcah, FLOW_CONTROL_ADDRESS_HIGH);
E1000_WRITE_REG(Fct, FLOW_CONTROL_TYPE);
E1000_WRITE_REG(Fcttv, FC_DEFAULT_TX_TIMER);
if (!(Adapter->FlowControl & FLOW_CONTROL_TRANSMIT_PAUSE)) {
E1000_WRITE_REG(Fcrtl, 0);
E1000_WRITE_REG(Fcrth, 0);
} else {
E1000_WRITE_REG(Fcrtl, (FC_DEFAULT_LO_THRESH | E1000_FCRTL_XONE));
E1000_WRITE_REG(Fcrth, FC_DEFAULT_HI_THRESH);
}
return (Status);
}
/* Callbackfunktion zum Aufraeume.
* Schliesst die Verbindung zur Datenbank */
static void clean_write(void *data){
PGconn *conn = data;
PQfinish(conn);
DEBUGOUT1("\nVerbindung Geschlossen \n");
}
int
at_configure(at_adapter *adapter)
{
at_hw * hw = &adapter->hw;
u32 value;
// DEBUGFUNC("at_configure() !\n");
// clear interrupt status
AT_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);
// set MAC Address
value = (((u32)hw->mac_addr[2]) << 24) |
(((u32)hw->mac_addr[3]) << 16) |
(((u32)hw->mac_addr[4]) << 8 ) |
(((u32)hw->mac_addr[5]) ) ;
AT_WRITE_REG(hw, REG_MAC_STA_ADDR, value);
value = (((u32)hw->mac_addr[0]) << 8 ) |
(((u32)hw->mac_addr[1]) ) ;
AT_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);
// tx / rx ring :
// HI base address
AT_WRITE_REG(
hw,
REG_DESC_BASE_ADDR_HI,
(u32)((adapter->ring_dma&0xffffffff00000000ULL) >>32));
// LO base address
AT_WRITE_REG(
hw,
REG_TXD_BASE_ADDR_LO,
(u32)(adapter->txd_dma&0x00000000ffffffffULL));
AT_WRITE_REG(
hw,
REG_TXS_BASE_ADDR_LO,
(u32)(adapter->txs_dma& 0x00000000ffffffffULL));
AT_WRITE_REG(hw,
REG_RXD_BASE_ADDR_LO,
(u32)(adapter->rxd_dma& 0x00000000ffffffffULL));
// element count
AT_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4));
AT_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size);
AT_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size);
DEBUGOUT1("txd ring size:%d, txs ring size:%d, rxd ring size:%d\n",
adapter->txd_ring_size/4,
adapter->txs_ring_size,
adapter->rxd_ring_size);
/* config Internal SRAM */
/*
AT_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end);
AT_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end);
*/
/* config IPG/IFG */
value =
(((u32)hw->ipgt&MAC_IPG_IFG_IPGT_MASK)
<<MAC_IPG_IFG_IPGT_SHIFT) |
(((u32)hw->min_ifg &MAC_IPG_IFG_MIFG_MASK)
<<MAC_IPG_IFG_MIFG_SHIFT) |
(((u32)hw->ipgr1&MAC_IPG_IFG_IPGR1_MASK)
<<MAC_IPG_IFG_IPGR1_SHIFT)|
(((u32)hw->ipgr2&MAC_IPG_IFG_IPGR2_MASK)
<<MAC_IPG_IFG_IPGR2_SHIFT);
AT_WRITE_REG(hw, REG_MAC_IPG_IFG, value);
// DEBUGOUT1("init ipg/ifg with 0x%x\n", value);
/* config Half-Duplex Control */
value =
((u32)hw->lcol&MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
(((u32)hw->max_retry&MAC_HALF_DUPLX_CTRL_RETRY_MASK)
<<MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
(0xa<<MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
(((u32)hw->jam_ipg&MAC_HALF_DUPLX_CTRL_JAMIPG_MASK)
<<MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
AT_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);
// DEBUGOUT1("init Half Duplex with 0x%x\n", value);
/* set Interrupt Moderator Timer */
AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt);
AT_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);
// DEBUGOUT1("init Irq Modurator Timer with 0x%x\n", adapter->imt);
/* set Interrupt Clear Timer */
AT_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict);
// DEBUGOUT1("init Irq Clear Timer with 0x%x\n", adapter->ict);
/* set MTU */
AT_WRITE_REG(hw, REG_MTU,
hw->max_frame_size +
ENET_HEADER_SIZE +
VLAN_SIZE +
ETHERNET_FCS_SIZE);
// DEBUGOUT1("init MTU with 0x%x\n", hw->max_frame_size);
/* 1590 */
AT_WRITE_REG(hw,
REG_TX_CUT_THRESH,
0x177);
/* flow control */
AT_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi);
AT_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo);
/* Init mailbox */
AT_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr);
AT_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr);
/* enable DMA read/write */
AT_WRITE_REGB(hw, REG_DMAR, DMAR_EN);
AT_WRITE_REGB(hw, REG_DMAW, DMAW_EN);
value = AT_READ_REG(&adapter->hw, REG_ISR);
if ((value&ISR_PHY_LINKDOWN) != 0) {
value = 1; // config failed
} else {
value = 0;
}
// clear all interrupt status
AT_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);
AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
return value;
}
s32
at_setup_ring_resources(at_adapter *adapter)
{
int size;
u8 offset = 0;
DEBUGFUNC("at_setup_ring_resources()\n");
/* real ring DMA buffer */
adapter->ring_size = size =
adapter->txd_ring_size * 1 + 7 // dword align
+ adapter->txs_ring_size * 4 + 7 // dword align
+ adapter->rxd_ring_size * 1536+ 127; // 128bytes align
adapter->memDesc = IOBufferMemoryDescriptor::withOptions(kIOMemoryPhysicallyContiguous|
kIODirectionOut|kIODirectionIn,
size,
PAGE_SIZE);
DbgPrint("Allocated memory for ring header %d\n",size);
if (!adapter->memDesc || (adapter->memDesc->prepare() != kIOReturnSuccess))
{
IOSleep(1500);
ErrPrint("Couldn't alloc memory for descriptor ring\n");
if (adapter->memDesc)
{
adapter->memDesc->release();
adapter->memDesc = NULL;
}
DEBUGOUT1("Couldn't alloc memory for descriptor ring, size = D%d\n", size);
return AT_ERR_ENOMEM;
}
IOByteCount dmaLength = 0;
adapter->ring_dma = adapter->memDesc->getPhysicalSegment(0, &dmaLength);
adapter->ring_vir_addr = adapter->memDesc->getBytesNoCopy();
DbgPrint("ring Physical segment address %X pointer %p length %d\n",
adapter->ring_dma, adapter->ring_vir_addr, dmaLength);
memset(adapter->ring_vir_addr, 0, adapter->ring_size);
// Init TXD Ring
adapter->txd_dma = adapter->ring_dma ;
offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0;
adapter->txd_dma += offset;
adapter->txd_ring = (tx_pkt_header_t*) ((u8*)adapter->ring_vir_addr + offset);
// Init TXS Ring
adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size;
offset = (adapter->txs_dma & 0x7) ? (8- (adapter->txs_dma & 0x7)) : 0;
adapter->txs_dma += offset;
adapter->txs_ring = (tx_pkt_status_t*)
(((u8*)adapter->txd_ring) + (adapter->txd_ring_size+offset));
// Init RXD Ring
adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size*4;
offset = (adapter->rxd_dma & 127) ? (128 - (adapter->rxd_dma & 127)) : 0;
if (offset > 7) {
offset -= 8;
} else {
offset += (128 - 8);
}
adapter->rxd_dma += offset;
adapter->rxd_ring = (rx_desc_t*)
(((u8*)adapter->txs_ring) +
(adapter->txs_ring_size*4 + offset));
// Read / Write Ptr Initialize:
// init_ring_ptrs(adapter);
return AT_SUCCESS;
}
HRESULT CAssemblyDownload::PreDownload(BOOL bCallCompleteAll, void **ppv)
{
HRESULT hr = S_OK;
IAssembly *pAssembly = NULL;
CCriticalSection cs(&_cs);
if ((!bCallCompleteAll && !ppv)) {
hr = E_INVALIDARG;
goto Exit;
}
// Check to make sure we're not in abort state
hr = cs.Lock();
if (FAILED(hr)) {
goto Exit;
}
// If someone aborted, then we would have already reported the abort
// back to the client. If it was the last client, we would have already
// transitioned to the DONE state as well. In this case, there's nothing
// to do.
if (_state == ADLSTATE_DONE) {
hr = _hrResult;
cs.Unlock();
goto Exit;
}
// Do a lookup in the cache and return an IAssembly object if found.
hr = _pDLMgr->PreDownloadCheck((void **)&pAssembly);
if (hr == S_OK) {
// We hit in doing the cache lookup
ASSERT(pAssembly);
cs.Unlock();
if (bCallCompleteAll) {
_hrResult = S_OK;
CompleteAll(pAssembly);
}
else {
*ppv = pAssembly;
pAssembly->AddRef();
}
pAssembly->Release();
hr = S_FALSE;
goto Exit;
}
else if (FAILED(hr)) {
// Catastrophic error doing predownload check
DEBUGOUT1(_pdbglog, 1, ID_FUSLOG_PREDOWNLOAD_FAILURE, hr);
cs.Unlock();
goto Exit;
}
hr = S_OK;
cs.Unlock();
Exit:
if (FAILED(hr) && hr != E_PENDING) {
_hrResult = hr;
}
return hr;
}
HRESULT CAssemblyDownload::DoSetup(LPOLESTR pwzFileName, const FILETIME *pftLastMod)
{
HRESULT hr = S_OK;
IUnknown *pUnk = NULL;
CCriticalSection cs(&_cs);
hr = cs.Lock();
if (FAILED(hr)) {
goto Exit;
}
if (_state == ADLSTATE_ABORT) {
_hrResult = HRESULT_FROM_WIN32(ERROR_CANCELLED);
hr = _hrResult;
cs.Unlock();
CompleteAll(NULL);
goto Exit;
}
cs.Unlock();
if (_pDLMgr) {
_hrResult = _pDLMgr->DoSetup(_pwzUrl, pwzFileName, pftLastMod, &pUnk);
if (_hrResult == S_FALSE) {
hr = cs.Lock();
if (FAILED(hr)) {
goto Exit;
}
_state = ADLSTATE_DOWNLOADING;
cs.Unlock();
hr = S_FALSE;
goto Exit;
}
}
else {
_hrResult = S_OK;
}
if (FAILED(_hrResult)) {
DEBUGOUT1(_pdbglog, 1, ID_FUSLOG_ASM_SETUP_FAILURE, _hrResult);
_pCodebaseList->RemoveAll();
}
// Store _hrResult, since it is possible that after CompleteAll, this
// object may be destroyed. See note in CompleteAll code.
hr = _hrResult;
CompleteAll(pUnk);
if (pUnk) {
pUnk->Release();
}
Exit:
return hr;
}
/**
* i40e_create_lan_hmc_object - allocate backing store for hmc objects
* @hw: pointer to the HW structure
* @info: pointer to i40e_hmc_create_obj_info struct
*
* This will allocate memory for PDs and backing pages and populate
* the sd and pd entries.
**/
enum i40e_status_code i40e_create_lan_hmc_object(struct i40e_hw *hw,
struct i40e_hmc_lan_create_obj_info *info)
{
enum i40e_status_code ret_code = I40E_SUCCESS;
struct i40e_hmc_sd_entry *sd_entry;
u32 pd_idx1 = 0, pd_lmt1 = 0;
u32 pd_idx = 0, pd_lmt = 0;
bool pd_error = false;
u32 sd_idx, sd_lmt;
u64 sd_size;
u32 i, j;
if (NULL == info) {
ret_code = I40E_ERR_BAD_PTR;
DEBUGOUT("i40e_create_lan_hmc_object: bad info ptr\n");
goto exit;
}
if (NULL == info->hmc_info) {
ret_code = I40E_ERR_BAD_PTR;
DEBUGOUT("i40e_create_lan_hmc_object: bad hmc_info ptr\n");
goto exit;
}
if (I40E_HMC_INFO_SIGNATURE != info->hmc_info->signature) {
ret_code = I40E_ERR_BAD_PTR;
DEBUGOUT("i40e_create_lan_hmc_object: bad signature\n");
goto exit;
}
if (info->start_idx >= info->hmc_info->hmc_obj[info->rsrc_type].cnt) {
ret_code = I40E_ERR_INVALID_HMC_OBJ_INDEX;
DEBUGOUT1("i40e_create_lan_hmc_object: returns error %d\n",
ret_code);
goto exit;
}
if ((info->start_idx + info->count) >
info->hmc_info->hmc_obj[info->rsrc_type].cnt) {
ret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;
DEBUGOUT1("i40e_create_lan_hmc_object: returns error %d\n",
ret_code);
goto exit;
}
/* find sd index and limit */
I40E_FIND_SD_INDEX_LIMIT(info->hmc_info, info->rsrc_type,
info->start_idx, info->count,
&sd_idx, &sd_lmt);
if (sd_idx >= info->hmc_info->sd_table.sd_cnt ||
sd_lmt > info->hmc_info->sd_table.sd_cnt) {
ret_code = I40E_ERR_INVALID_SD_INDEX;
goto exit;
}
/* find pd index */
I40E_FIND_PD_INDEX_LIMIT(info->hmc_info, info->rsrc_type,
info->start_idx, info->count, &pd_idx,
&pd_lmt);
/* This is to cover for cases where you may not want to have an SD with
* the full 2M memory but something smaller. By not filling out any
* size, the function will default the SD size to be 2M.
*/
if (info->direct_mode_sz == 0)
sd_size = I40E_HMC_DIRECT_BP_SIZE;
else
sd_size = info->direct_mode_sz;
/* check if all the sds are valid. If not, allocate a page and
* initialize it.
*/
for (j = sd_idx; j < sd_lmt; j++) {
/* update the sd table entry */
ret_code = i40e_add_sd_table_entry(hw, info->hmc_info, j,
info->entry_type,
sd_size);
if (I40E_SUCCESS != ret_code)
goto exit_sd_error;
sd_entry = &info->hmc_info->sd_table.sd_entry[j];
if (I40E_SD_TYPE_PAGED == sd_entry->entry_type) {
/* check if all the pds in this sd are valid. If not,
* allocate a page and initialize it.
*/
/* find pd_idx and pd_lmt in this sd */
pd_idx1 = max(pd_idx, (j * I40E_HMC_MAX_BP_COUNT));
pd_lmt1 = min(pd_lmt,
((j + 1) * I40E_HMC_MAX_BP_COUNT));
for (i = pd_idx1; i < pd_lmt1; i++) {
/* update the pd table entry */
ret_code = i40e_add_pd_table_entry(hw,
info->hmc_info,
i);
if (I40E_SUCCESS != ret_code) {
pd_error = true;
break;
}
}
if (pd_error) {
/* remove the backing pages from pd_idx1 to i */
while (i && (i > pd_idx1)) {
i40e_remove_pd_bp(hw, info->hmc_info,
(i - 1));
i--;
}
}
}
if (!sd_entry->valid) {
sd_entry->valid = true;
switch (sd_entry->entry_type) {
case I40E_SD_TYPE_PAGED:
I40E_SET_PF_SD_ENTRY(hw,
sd_entry->u.pd_table.pd_page_addr.pa,
j, sd_entry->entry_type);
break;
case I40E_SD_TYPE_DIRECT:
I40E_SET_PF_SD_ENTRY(hw, sd_entry->u.bp.addr.pa,
j, sd_entry->entry_type);
break;
default:
ret_code = I40E_ERR_INVALID_SD_TYPE;
goto exit;
}
}
}
goto exit;
exit_sd_error:
/* cleanup for sd entries from j to sd_idx */
while (j && (j > sd_idx)) {
sd_entry = &info->hmc_info->sd_table.sd_entry[j - 1];
switch (sd_entry->entry_type) {
case I40E_SD_TYPE_PAGED:
pd_idx1 = max(pd_idx,
((j - 1) * I40E_HMC_MAX_BP_COUNT));
pd_lmt1 = min(pd_lmt, (j * I40E_HMC_MAX_BP_COUNT));
for (i = pd_idx1; i < pd_lmt1; i++) {
i40e_remove_pd_bp(hw, info->hmc_info, i);
}
i40e_remove_pd_page(hw, info->hmc_info, (j - 1));
break;
case I40E_SD_TYPE_DIRECT:
i40e_remove_sd_bp(hw, info->hmc_info, (j - 1));
break;
default:
ret_code = I40E_ERR_INVALID_SD_TYPE;
break;
}
j--;
}
exit:
return ret_code;
}
HRESULT CAssemblyDownload::GetNextCodebase(BOOL *pbIsFileUrl, LPWSTR wzFilePath,
DWORD cbLen)
{
HRESULT hr = S_OK;
LPWSTR wzNextCodebase = NULL;
DWORD cbCodebase;
DWORD dwSize;
BOOL bIsFileUrl = FALSE;
ASSERT(pbIsFileUrl && wzFilePath);
*pbIsFileUrl = FALSE;
for (;;) {
cbCodebase = 0;
hr = _pCodebaseList->GetCodebase(0, NULL, &cbCodebase);
if (hr != HRESULT_FROM_WIN32(ERROR_INSUFFICIENT_BUFFER)) {
// could not get codebase
hr = HRESULT_FROM_WIN32(ERROR_NO_MORE_ITEMS);
goto Exit;
}
wzNextCodebase = NEW(WCHAR[cbCodebase]);
if (!wzNextCodebase) {
hr = E_OUTOFMEMORY;
goto Exit;
}
hr = _pCodebaseList->GetCodebase(0, wzNextCodebase, &cbCodebase);
if (FAILED(hr)) {
goto Exit;
}
hr = _pCodebaseList->RemoveCodebase(0);
if (FAILED(hr)) {
goto Exit;
}
// Check if we are a UNC or file:// URL. If we are, we don't have
// to do a download, and can call setup right away.
bIsFileUrl = UrlIsW(wzNextCodebase, URLIS_FILEURL);
if (bIsFileUrl) {
dwSize = cbLen;
if (FAILED(PathCreateFromUrlWrap(wzNextCodebase, wzFilePath, &dwSize, 0))) {
wzFilePath[0] = L'\0';
}
if (GetFileAttributes(wzFilePath) == (DWORD) -1) {
// File doesn't exist. Try the next URL.
DEBUGOUT1(_pdbglog, 0, ID_FUSLOG_ATTEMPT_NEW_DOWNLOAD, wzNextCodebase);
ReportProgress(0, 0, 0, ASM_NOTIFICATION_ATTEMPT_NEXT_CODEBASE,
(LPCWSTR)wzNextCodebase, _hrResult);
_hrResult = HRESULT_FROM_WIN32(ERROR_FILE_NOT_FOUND);
SAFEDELETEARRAY(wzNextCodebase);
continue;
}
}
else {
hr = HRESULT_FROM_WIN32(ERROR_NOT_SUPPORTED);
goto Exit;
}
break;
}
*pbIsFileUrl = bIsFileUrl;
PrepNextDownload(wzNextCodebase);
Exit:
SAFEDELETEARRAY(wzNextCodebase);
return hr;
}
/**
* i40e_delete_hmc_object - remove hmc objects
* @hw: pointer to the HW structure
* @info: pointer to i40e_hmc_delete_obj_info struct
*
* This will de-populate the SDs and PDs. It frees
* the memory for PDS and backing storage. After this function is returned,
* caller should deallocate memory allocated previously for
* book-keeping information about PDs and backing storage.
**/
enum i40e_status_code i40e_delete_lan_hmc_object(struct i40e_hw *hw,
struct i40e_hmc_lan_delete_obj_info *info)
{
enum i40e_status_code ret_code = I40E_SUCCESS;
struct i40e_hmc_pd_table *pd_table;
u32 pd_idx, pd_lmt, rel_pd_idx;
u32 sd_idx, sd_lmt;
u32 i, j;
if (NULL == info) {
ret_code = I40E_ERR_BAD_PTR;
DEBUGOUT("i40e_delete_hmc_object: bad info ptr\n");
goto exit;
}
if (NULL == info->hmc_info) {
ret_code = I40E_ERR_BAD_PTR;
DEBUGOUT("i40e_delete_hmc_object: bad info->hmc_info ptr\n");
goto exit;
}
if (I40E_HMC_INFO_SIGNATURE != info->hmc_info->signature) {
ret_code = I40E_ERR_BAD_PTR;
DEBUGOUT("i40e_delete_hmc_object: bad hmc_info->signature\n");
goto exit;
}
if (NULL == info->hmc_info->sd_table.sd_entry) {
ret_code = I40E_ERR_BAD_PTR;
DEBUGOUT("i40e_delete_hmc_object: bad sd_entry\n");
goto exit;
}
if (NULL == info->hmc_info->hmc_obj) {
ret_code = I40E_ERR_BAD_PTR;
DEBUGOUT("i40e_delete_hmc_object: bad hmc_info->hmc_obj\n");
goto exit;
}
if (info->start_idx >= info->hmc_info->hmc_obj[info->rsrc_type].cnt) {
ret_code = I40E_ERR_INVALID_HMC_OBJ_INDEX;
DEBUGOUT1("i40e_delete_hmc_object: returns error %d\n",
ret_code);
goto exit;
}
if ((info->start_idx + info->count) >
info->hmc_info->hmc_obj[info->rsrc_type].cnt) {
ret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;
DEBUGOUT1("i40e_delete_hmc_object: returns error %d\n",
ret_code);
goto exit;
}
I40E_FIND_PD_INDEX_LIMIT(info->hmc_info, info->rsrc_type,
info->start_idx, info->count, &pd_idx,
&pd_lmt);
for (j = pd_idx; j < pd_lmt; j++) {
sd_idx = j / I40E_HMC_PD_CNT_IN_SD;
if (I40E_SD_TYPE_PAGED !=
info->hmc_info->sd_table.sd_entry[sd_idx].entry_type)
continue;
rel_pd_idx = j % I40E_HMC_PD_CNT_IN_SD;
pd_table =
&info->hmc_info->sd_table.sd_entry[sd_idx].u.pd_table;
if (pd_table->pd_entry[rel_pd_idx].valid) {
ret_code = i40e_remove_pd_bp(hw, info->hmc_info, j);
if (I40E_SUCCESS != ret_code)
goto exit;
}
}
/* find sd index and limit */
I40E_FIND_SD_INDEX_LIMIT(info->hmc_info, info->rsrc_type,
info->start_idx, info->count,
&sd_idx, &sd_lmt);
if (sd_idx >= info->hmc_info->sd_table.sd_cnt ||
sd_lmt > info->hmc_info->sd_table.sd_cnt) {
ret_code = I40E_ERR_INVALID_SD_INDEX;
goto exit;
}
for (i = sd_idx; i < sd_lmt; i++) {
if (!info->hmc_info->sd_table.sd_entry[i].valid)
continue;
switch (info->hmc_info->sd_table.sd_entry[i].entry_type) {
case I40E_SD_TYPE_DIRECT:
ret_code = i40e_remove_sd_bp(hw, info->hmc_info, i);
if (I40E_SUCCESS != ret_code)
goto exit;
break;
case I40E_SD_TYPE_PAGED:
ret_code = i40e_remove_pd_page(hw, info->hmc_info, i);
if (I40E_SUCCESS != ret_code)
goto exit;
break;
default:
break;
}
}
exit:
return ret_code;
}
/**
* ixgbe_setup_fc_82598 - Configure flow control settings
* @hw: pointer to hardware structure
* @packetbuf_num: packet buffer number (0-7)
*
* Configures the flow control settings based on SW configuration. This
* function is used for 802.3x flow control configuration only.
**/
int32_t ixgbe_setup_fc_82598(struct ixgbe_hw *hw, int32_t packetbuf_num)
{
uint32_t frctl_reg;
uint32_t rmcs_reg;
if (packetbuf_num < 0 || packetbuf_num > 7) {
DEBUGOUT1("Invalid packet buffer number [%d], expected range is"
" 0-7\n", packetbuf_num);
panic("ixgbe");
}
frctl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
frctl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
/*
* 10 gig parts do not have a word in the EEPROM to determine the
* default flow control setting, so we explicitly set it to full.
*/
if (hw->fc.type == ixgbe_fc_default)
hw->fc.type = ixgbe_fc_full;
/*
* We want to save off the original Flow Control configuration just in
* case we get disconnected and then reconnected into a different hub
* or switch with different Flow Control capabilities.
*/
hw->fc.original_type = hw->fc.type;
/*
* The possible values of the "flow_control" parameter are:
* 0: Flow control is completely disabled
* 1: Rx flow control is enabled (we can receive pause frames but not
* send pause frames).
* 2: Tx flow control is enabled (we can send pause frames but we do not
* support receiving pause frames)
* 3: Both Rx and Tx flow control (symmetric) are enabled.
* other: Invalid.
*/
switch (hw->fc.type) {
case ixgbe_fc_none:
break;
case ixgbe_fc_rx_pause:
/*
* Rx Flow control is enabled,
* and Tx Flow control is disabled.
*/
frctl_reg |= IXGBE_FCTRL_RFCE;
break;
case ixgbe_fc_tx_pause:
/*
* Tx Flow control is enabled, and Rx Flow control is disabled,
* by a software over-ride.
*/
rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
break;
case ixgbe_fc_full:
/*
* Flow control (both Rx and Tx) is enabled by a software
* over-ride.
*/
frctl_reg |= IXGBE_FCTRL_RFCE;
rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
break;
default:
/* We should never get here. The value should be 0-3. */
DEBUGOUT("Flow control param set incorrectly\n");
panic("ixgbe");
break;
}
/* Enable 802.3x based flow control settings. */
IXGBE_WRITE_REG(hw, IXGBE_FCTRL, frctl_reg);
IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
/*
* Check for invalid software configuration, zeros are completely
* invalid for all parameters used past this point, and if we enable
* flow control with zero water marks, we blast flow control packets.
*/
if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
DEBUGOUT("Flow control structure initialized incorrectly\n");
return IXGBE_ERR_INVALID_LINK_SETTINGS;
}
/*
* We need to set up the Receive Threshold high and low water
* marks as well as (optionally) enabling the transmission of
* XON frames.
*/
if (hw->fc.type & ixgbe_fc_tx_pause) {
if (hw->fc.send_xon) {
IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
(hw->fc.low_water | IXGBE_FCRTL_XONE));
} else {
IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
hw->fc.low_water);
}
IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
(hw->fc.high_water)|IXGBE_FCRTH_FCEN);
}
IXGBE_WRITE_REG(hw, IXGBE_FCTTV(0), hw->fc.pause_time);
IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
return IXGBE_SUCCESS;
}
