int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg) { u32 v, i; int ret = GMACSL_RET_OK; if (port >= DEVICE_N_GMACSL_PORTS) return GMACSL_RET_INVALID_PORT; if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) { cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN; ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG; } /* Must wait if the device is undergoing reset */ for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) != CPGMAC_REG_RESET_VAL_RESET) break; } if (i == DEVICE_EMACSL_RESET_POLL_COUNT) return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE; writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN); writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL); #ifndef CONFIG_SOC_K2HK /* Map RX packet flow priority to 0 */ writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP); #endif return ret; }
int mac_sl_reset(u32 port) { u32 i, v; if (port >= DEVICE_N_GMACSL_PORTS) return GMACSL_RET_INVALID_PORT; /* Set the soft reset bit */ writel(CPGMAC_REG_RESET_VAL_RESET, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); /* Wait for the bit to clear */ for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) != CPGMAC_REG_RESET_VAL_RESET) return GMACSL_RET_OK; } /* Timeout on the reset */ return GMACSL_RET_WARN_RESET_INCOMPLETE; }
keystone2_eth_gigabit_enable(struct udevice *dev) { struct ks2_eth_priv *priv = dev_get_priv(dev); u_int16_t data; if (priv->has_mdio) { data = keystone2_mdio_read(priv->mdio_bus, priv->phy_addr, MDIO_DEVAD_NONE, 0); /* speed selection MSB */ if (!(data & (1 << 6))) return; } /* * Check if link detected is giga-bit * If Gigabit mode detected, enable gigbit in MAC */ writel(readl(DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL) | EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE, DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL); }
/******************************************************************************************* * FUNCTION PURPOSE: Configure the gmac sliver ******************************************************************************************* * DESCRIPTION: The emac sliver is configured. *******************************************************************************************/ SINT16 hwGmacSlConfig (UINT16 port, hwGmacSlCfg_t *cfg) { UINT32 v; UINT32 i; SINT16 ret = GMACSL_RET_OK; if (port >= DEVICE_N_GMACSL_PORTS) return (GMACSL_RET_INVALID_PORT); if (cfg->maxRxLen > CPGMAC_REG_MAXLEN_LEN) { cfg->maxRxLen = CPGMAC_REG_MAXLEN_LEN; ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG; } /* Must wait if the device is undergoing reset */ for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { v = DEVICE_REG32_R (DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); if ( (v & CPGMAC_REG_RESET_VAL_RESET_MASK) != CPGMAC_REG_RESET_VAL_RESET) break; } if (i == DEVICE_EMACSL_RESET_POLL_COUNT) return (GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE); DEVICE_REG32_W(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN, cfg->maxRxLen); DEVICE_REG32_W(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL, cfg->ctl); return (ret); } /* hwGmacSlConfig */
/******************************************************************************************** * FUNCTION PURPOSE: Reset the the gmac sliver ******************************************************************************************** * DESCRIPTION: Soft reset is set and polled until clear, or until a timeout occurs ********************************************************************************************/ SINT16 hwGmacSlReset (UINT16 port) { UINT32 i; UINT32 v; if (port >= DEVICE_N_GMACSL_PORTS) return (GMACSL_RET_INVALID_PORT); /* Set the soft reset bit */ DEVICE_REG32_W (DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET, CPGMAC_REG_RESET_VAL_RESET); /* Wait for the bit to clear */ for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { v = DEVICE_REG32_R (DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); if ( (v & CPGMAC_REG_RESET_VAL_RESET_MASK) != CPGMAC_REG_RESET_VAL_RESET) return (GMACSL_RET_OK); } /* Timeout on the reset */ return (GMACSL_RET_WARN_RESET_INCOMPLETE); } /* hwGmacSlReset */