int OVLStop() {
DISP_REG_SET(DISP_REG_OVL_INTEN, 0x00);
DISP_REG_SET(DISP_REG_OVL_EN, 0x00);
DISP_REG_SET(DISP_REG_OVL_INTSTA, 0x00);
return 0;
}
int OVLLayerSwitch(unsigned layer, bool en) {
ASSERT(layer<=3);
switch(layer) {
case 0:
DISP_REG_SET_FIELD(SRC_CON_FLD_L0_EN, DISP_REG_OVL_SRC_CON, en);
DISP_REG_SET(DISP_REG_OVL_RDMA0_CTRL, 0);
break;
case 1:
DISP_REG_SET_FIELD(SRC_CON_FLD_L1_EN, DISP_REG_OVL_SRC_CON, en);
DISP_REG_SET(DISP_REG_OVL_RDMA1_CTRL, 0);
break;
case 2:
DISP_REG_SET_FIELD(SRC_CON_FLD_L2_EN, DISP_REG_OVL_SRC_CON, en);
DISP_REG_SET(DISP_REG_OVL_RDMA2_CTRL, 0);
break;
case 3:
DISP_REG_SET_FIELD(SRC_CON_FLD_L3_EN, DISP_REG_OVL_SRC_CON, en);
DISP_REG_SET(DISP_REG_OVL_RDMA3_CTRL, 0);
break;
default:
printk("error: invalid layer=%d \n", layer); // invalid layer
ASSERT(0);
}
return 0;
}
static void aal_test_ink(const char *cmd)
{
int en = (cmd[0] - '0');
const unsigned long cabc_04 = DISP_AAL_CABC_00 + 0x4 * 4;
switch (en) {
case 1:
DISP_REG_SET(NULL, cabc_04, (1 << 31) | (511 << 18));
break;
case 2:
DISP_REG_SET(NULL, cabc_04, (1 << 31) | (511 << 9));
break;
case 3:
DISP_REG_SET(NULL, cabc_04, (1 << 31) | (511 << 0));
break;
case 4:
DISP_REG_SET(NULL, cabc_04, (1 << 31) | (511 << 18) | (511 << 9) | 511);
break;
default:
DISP_REG_SET(NULL, cabc_04, 0);
break;
}
disp_aal_trigger_refresh();
}
int OVLStart(void) {
DISP_REG_SET(DISP_REG_OVL_INTEN, 0x0f);
DISP_REG_SET(DISP_REG_OVL_EN, 0x01);
return 0;
}
int disp_path_config_layer_addr(unsigned int layer, unsigned int addr)
{
unsigned int reg_addr;
printf("[DDP]disp_path_config_layer_addr(), layer=%d, addr=0x%x\n ", layer, addr);
// disp_path_get_mutex();
switch(layer)
{
case 0:
DISP_REG_SET(DISP_REG_OVL_L0_ADDR, addr);
reg_addr = DISP_REG_OVL_L0_ADDR;
break;
case 1:
DISP_REG_SET(DISP_REG_OVL_L1_ADDR, addr);
reg_addr = DISP_REG_OVL_L1_ADDR;
break;
case 2:
DISP_REG_SET(DISP_REG_OVL_L2_ADDR, addr);
reg_addr = DISP_REG_OVL_L2_ADDR;
break;
case 3:
DISP_REG_SET(DISP_REG_OVL_L3_ADDR, addr);
reg_addr = DISP_REG_OVL_L3_ADDR;
break;
default:
printf("[DDP] error! error: unknow layer=%d \n", layer);
}
printf("[DDP]disp_path_config_layer_addr() done, addr=0x%x \n", DISP_REG_GET(reg_addr));
// disp_path_release_mutex();
return 0;
}
int disp_bls_enable_irq(unsigned int value)
{
DISP_REG_SET(DISP_REG_BLS_INTSTA, 0x00);
DISP_REG_SET(DISP_REG_BLS_INTEN, value);
return 0;
}
int ovl_start(DISP_MODULE_ENUM module, void *handle)
{
int idx = ovl_index(module);
int idx_offset = idx*DISP_OVL_INDEX_OFFSET;
DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_EN, 0x01);
int enable_ovl_irq = 1;
#if defined(CONFIG_TRUSTONIC_TEE_SUPPORT) && defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
enable_ovl_irq = 1;
#else
if(gEnableIRQ==1)
enable_ovl_irq = 1;
else
enable_ovl_irq = 0;
#endif
if(enable_ovl_irq)
DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_INTEN, 0x1e2);
else
DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_INTEN, 0x1e0);
DISP_REG_SET_FIELD(handle, DATAPATH_CON_FLD_LAYER_SMI_ID_EN,
idx_offset+DISP_REG_OVL_DATAPATH_CON, 0x1);
return 0;
}
int ovl_layer_switch(DISP_MODULE_ENUM module,
unsigned layer,
unsigned int en,
void *handle)
{
int idx = ovl_index(module);
int idx_offset = idx*DISP_OVL_INDEX_OFFSET;
ASSERT(layer <= 3);
// DDPDBG("ovl%d,layer %d,enable %d\n", idx, layer, en);
switch (layer) {
case 0:
DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_RDMA0_CTRL, en);
break;
case 1:
DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_RDMA1_CTRL, en);
break;
case 2:
DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_RDMA2_CTRL, en);
break;
case 3:
DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_RDMA3_CTRL, en);
break;
default:
DDPERR("invalid layer=%d\n", layer);
ASSERT(0);
}
return 0;
}
/* stop module */
int SCLStop(void)
{
DISP_REG_SET_FIELD(DSCL_CTRL_FLD_SCL_EN, DISP_REG_SCL_CTRL, 0);
DISP_REG_SET(DISP_REG_SCL_INTEN, 0);
DISP_REG_SET(DISP_REG_SCL_INTSTA, 0);
return 0;
}
int disp_bls_set_backlight(unsigned int level)
{
printf("[DDP] disp_bls_set_backlight: %d, CG = 0x%x, BLS_EN = 0x%x, PWM_DUTY = %d\n",
level,
DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON0),
DISP_REG_GET(DISP_REG_BLS_EN),
DISP_REG_GET(DISP_REG_BLS_PWM_DUTY));
if (level && (!(DISP_REG_GET(DISP_REG_BLS_EN) & 0x10000)))
{
disp_bls_config();
}
#ifdef USE_DISP_BLS_MUTEX
disp_bls_get_mutex();
#else
DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x3);
#endif
DISP_REG_SET(DISP_REG_BLS_PWM_DUTY, brightness_mapping(level));
printf("[DDP] PWM_DUTY: %x\n", DISP_REG_GET(DISP_REG_BLS_PWM_DUTY));
#ifdef USE_DISP_BLS_MUTEX
disp_bls_release_mutex();
#else
DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x0);
#endif
return 0;
}
void disp_bls_init(unsigned int srcWidth, unsigned int srcHeight)
{
struct cust_mt65xx_led *cust_led_list = get_cust_led_list();
struct cust_mt65xx_led *cust = NULL;
struct PWM_config *config_data = NULL;
if(cust_led_list)
{
cust = &cust_led_list[MT65XX_LED_TYPE_LCD];
if((strcmp(cust->name,"lcd-backlight") == 0) && (cust->mode == MT65XX_LED_MODE_CUST_BLS_PWM))
{
config_data = &cust->config_data;
if (config_data->clock_source >= 0 && config_data->clock_source <= 3)
{
unsigned int regVal = DISP_REG_GET(CLK_CFG_1);
DISP_REG_SET(CLK_CFG_1, (regVal & ~0x3) | config_data->clock_source);
printf("disp_bls_init : CLK_CFG_1 0x%x => 0x%x\n", regVal, DISP_REG_GET(CLK_CFG_1));
}
gPWMDiv = (config_data->div == 0) ? PWM_DEFAULT_DIV_VALUE : config_data->div;
gPWMDiv &= 0x3FF;
printf("disp_bls_init : PWM config data (%d,%d)\n", config_data->clock_source, config_data->div);
}
}
printf("[DDP] disp_bls_init : srcWidth = %d, srcHeight = %d\n", srcWidth, srcHeight);
printf("[DDP] disp_bls_init : CG = 0x%x, BLS_EN = 0x%x, PWM_DUTY = %d\n",
DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON0),
DISP_REG_GET(DISP_REG_BLS_EN),
DISP_REG_GET(DISP_REG_BLS_PWM_DUTY));
DISP_REG_SET(DISP_REG_BLS_SRC_SIZE, (srcHeight << 16) | srcWidth);
DISP_REG_SET(DISP_REG_BLS_PWM_DUTY, 0);
DISP_REG_SET(DISP_REG_BLS_PWM_CON, 0x0 | (gPWMDiv << 16));
DISP_REG_SET(DISP_REG_BLS_EN, 0x00010000);
}
int RDMAStop(unsigned idx) {
ASSERT(idx <= 2);
DISP_REG_SET_FIELD(GLOBAL_CON_FLD_ENGINE_EN, idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON, 0);
DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_INT_ENABLE, 0);
DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_INT_STATUS, 0);
return 0;
}
int ddp_mutex_reset(int mutex_id, void * handle)
{
DDPDBG("mutex %d reset\n", mutex_id);
DISP_REG_SET(handle,DISP_REG_CONFIG_MUTEX_RST(mutex_id),1);
DISP_REG_SET(handle,DISP_REG_CONFIG_MUTEX_RST(mutex_id),0);
return 0;
}
static int wdma_start(DISP_MODULE_ENUM module,void * handle)
{
unsigned int idx = wdma_index(module);
DISP_REG_SET(handle,idx*DISP_WDMA_INDEX_OFFSET+DISP_REG_WDMA_INTEN, 0x03);
DISP_REG_SET(handle,idx*DISP_WDMA_INDEX_OFFSET+DISP_REG_WDMA_EN, 0x01);
return 0;
}
int OVLStop(DISP_MODULE_ENUM module,void * handle) {
int idx = ovl_index(module);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+DISP_REG_OVL_INTEN, 0x00);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+DISP_REG_OVL_EN, 0x00);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+DISP_REG_OVL_INTSTA, 0x00);
return 0;
}
int WDMAStart(unsigned idx) {
DISP_REG_SET(DISP_REG_WDMA_INTEN, 0x01);
DISP_REG_SET(DISP_REG_WDMA_EN, 0x01);
return 0;
}
int WDMAStop(unsigned idx) {
DISP_REG_SET(DISP_REG_WDMA_INTEN, 0x00);
DISP_REG_SET(DISP_REG_WDMA_EN, 0x00);
return 0;
}
int WDMAStart(unsigned idx) {
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_INTEN, 0x03);
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_EN, 0x01);
return 0;
}
int disp_bls_set_backlight(unsigned int level)
{
unsigned int mapped_level;
DISP_MSG("disp_bls_set_backlight: %d, gBLSPowerOn = %d\n", level, gBLSPowerOn);
mutex_lock(&backlight_mutex);
if(level && !clock_is_on(MT_CG_PWM_MM_SW_CG))
enable_clock(MT_CG_PWM_MM_SW_CG, "DDP");
if (level && !clock_is_on(MT_CG_MDP_BLS_26M_SW_CG))
{
// remove CG control to DDP path
ASSERT(0);
if (!gBLSPowerOn)
{
// config BLS parameter
disp_bls_config();
}
}
#ifdef USE_DISP_BLS_MUTEX
disp_bls_get_mutex();
#else
DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x3);
#endif
mapped_level = brightness_mapping(level);
DISP_MSG("after mapping, mapped_level: %d\n", mapped_level);
DISP_REG_SET(DISP_REG_BLS_PWM_DUTY, mapped_level);
if (mapped_level) // enable PWM generator
DISP_REG_SET(DISP_REG_BLS_EN, DISP_REG_GET(DISP_REG_BLS_EN) | 0x10000);
else // disable PWM generator
DISP_REG_SET(DISP_REG_BLS_EN, DISP_REG_GET(DISP_REG_BLS_EN) & 0xFFFEFFFF);
DISP_MSG("after SET, PWM_DUTY: %d\n", DISP_REG_GET(DISP_REG_BLS_PWM_DUTY));
#ifdef USE_DISP_BLS_MUTEX
disp_bls_release_mutex();
#else
DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x0);
#endif
if(!level && clock_is_on(MT_CG_PWM_MM_SW_CG))
disable_clock(MT_CG_PWM_MM_SW_CG, "DDP");
if (!level && gBLSPowerOn)
{
DISP_MSG("disp_bls_set_backlight: disable clock\n");
// disable_clock(MT_CG_DISP0_SMI_LARB0 , "DDP");
gBLSPowerOn = 0;
}
mutex_unlock(&backlight_mutex);
return 0;
}
int OVLStart(DISP_MODULE_ENUM module,void * handle) {
int idx = ovl_index(module);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+DISP_REG_OVL_INTEN, 0x0E);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+DISP_REG_OVL_EN, 0x01);
DISP_REG_SET_FIELD(handle,DATAPATH_CON_FLD_LAYER_SMI_ID_EN,
idx*DISP_INDEX_OFFSET+DISP_REG_OVL_DATAPATH_CON,0x1);
return 0;
}
int rdma_stop(DISP_MODULE_ENUM module,void * handle) {
unsigned int idx = rdma_index(module);
ASSERT(idx <= 2);
DISP_REG_SET_FIELD(handle,GLOBAL_CON_FLD_ENGINE_EN, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON, 0);
DISP_REG_SET(handle,idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_INT_ENABLE, 0);
DISP_REG_SET(handle,idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_INT_STATUS, 0);
return 0;
}
static void disp_ccorr_init(disp_ccorr_id_t id, unsigned int width, unsigned int height, void *cmdq)
{
DISP_REG_SET(cmdq, DISP_REG_CCORR_SIZE, (width << 16) | height);
#ifndef CONFIG_FPGA_EARLY_PORTING
disp_ccorr_write_coef_reg(cmdq, id, 1);
#else
DISP_REG_SET(cmdq, DISP_REG_CCORR_EN, 1);
#endif
}
int WDMAStop(unsigned idx) {
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_INTEN, 0x00);
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_EN, 0x00);
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_INTSTA, 0x00);
return 0;
}
int WDMAConfigUV(unsigned idx, unsigned int uAddr, unsigned int vAddr, unsigned int dstWidth)
{
unsigned int bpp=1;
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_DST_U_ADDR, uAddr);
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_DST_V_ADDR, vAddr);
DISP_REG_SET_FIELD(WDMA_BUF_ADDR_FLD_UV_Pitch, idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_DST_UV_PITCH, dstWidth * bpp/2);
return 0;
}
int ovl_stop(DISP_MODULE_ENUM module, void *handle)
{
int idx = ovl_index(module);
int idx_offset = idx*DISP_OVL_INDEX_OFFSET;
DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_INTEN, 0x00);
DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_EN, 0x00);
DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_INTSTA, 0x00);
return 0;
}
int disp_bls_reset(void)
{
unsigned int regValue;
regValue = DISP_REG_GET(DISP_REG_BLS_RST);
DISP_REG_SET(DISP_REG_BLS_RST, regValue | 0x1);
DISP_REG_SET(DISP_REG_BLS_RST, regValue & (~0x1));
return 0;
}
int ddp_mutex_clear(int mutex_id, void * handle)
{
DDPDBG("mutex %d clear\n", mutex_id);
DISP_REG_SET(handle,DISP_REG_CONFIG_MUTEX_MOD(mutex_id),0);
DISP_REG_SET(handle,DISP_REG_CONFIG_MUTEX_SOF(mutex_id),0);
/*reset mutex*/
ddp_mutex_reset(mutex_id,handle);
return 0;
}
int WDMAReset(unsigned idx) {
unsigned int delay_cnt = 0;
//WDMA_RST = 0x00;
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_RST , 0x01); // soft reset
while((DISP_REG_GET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_FLOW_CTRL_DBG)&0x1) != 0x1)
{
delay_cnt++;
if(delay_cnt>10000)
{
printk("[DDP] error, WDMAReset(%d) timeout! \n", idx);
break;
}
}
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_RST , 0x00);
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_CFG , 0x00);
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_SRC_SIZE , 0x00);
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_CLIP_SIZE , 0x00);
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_CLIP_COORD , 0x00);
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_DST_ADDR , 0x00);
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_DST_W_IN_BYTE , 0x00);
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_ALPHA , 0x00); // clear regs
return 0;
}
int WDMAReset(unsigned idx) {
unsigned int delay_cnt = 0;
static unsigned int wdma_timeout_cnt = 0;
//WDMA_RST = 0x00;
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_RST , 0x01); // soft reset
while((DISP_REG_GET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_FLOW_CTRL_DBG)&0x1) != 0x1)
{
delay_cnt++;
if(delay_cnt>10000)
{
printk("[DDP] error, WDMAReset(%d) timeout! wdma_timeout_cnt=%d \n", idx, wdma_timeout_cnt++);
WDMADumpHidenReg(idx);
disp_dump_reg(DISP_MODULE_WDMA0);
smi_dumpDebugMsg();
break;
}
}
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_RST , 0x00);
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_CFG , 0x00);
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_SRC_SIZE , 0x00);
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_CLIP_SIZE , 0x00);
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_CLIP_COORD , 0x00);
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_DST_ADDR , 0x00);
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_DST_W_IN_BYTE , 0x00);
DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_ALPHA , 0x00); // clear regs
return 0;
}
void disp_pq_init(void)
{
spin_lock_init(&gHistLock);
DISP_REG_SET(DISP_REG_PQ_CTRL, 0x00000002);
DISP_REG_SET(DISP_REG_PQ_CTRL, 0x00000000);
DISP_REG_SET(DISP_REG_PQ_INTEN, 0x00000007);
DISP_REG_SET(DISP_REG_PQ_CTRL, 0x00000001);
DISP_REG_SET(DISP_REG_PQ_C_HIST_CON, 0);
}