static int omap3_setup_dma(SIM_HBA *hba, paddr_t paddr, int len, int dir)
{
SIM_MMC_EXT *ext;
omap3_ext_t *omap3;
dma4_param *param;
ext = (SIM_MMC_EXT *)hba->ext;
omap3 = (omap3_ext_t *)ext->handle;
//
// Initialize Tx DMA channel
//
param = (dma4_param *)(omap3->dma_base + DMA4_CCR(omap3->dma_chnl));
len = omap3_setup_pio(hba, len, dir);
if (len > 0) {
// Clear all status bits
param->csr = 0x1FFE;
param->cen = len >> 2;
param->cfn = 1; // Number of frames
param->cse = 1;
param->cde = 1;
param->cicr = 0; // We don't want any interrupts
if (dir == MMC_DIR_IN) {
// setup receive SDMA channel
param->csdp = (2 << 0) // DATA_TYPE = 0x2: 32 bit element
| (0 << 2) // RD_ADD_TRSLT = 0: Not used
| (0 << 6) // SRC_PACKED = 0x0: Cannot pack source data
| (0 << 7) // SRC_BURST_EN = 0x0: Cannot burst source
| (0 << 9) // WR_ADD_TRSLT = 0: Undefined
| (0 << 13) // DST_PACKED = 0x0: No packing
| (3 << 14) // DST_BURST_EN = 0x3: Burst at 16x32 bits
| (1 << 16) // WRITE_MODE = 0x1: Write posted
| (0 << 18) // DST_ENDIAN_LOCK = 0x0: Endianness adapt
| (0 << 19) // DST_ENDIAN = 0x0: Little Endian type at destination
| (0 << 20) // SRC_ENDIAN_LOCK = 0x0: Endianness adapt
| (0 << 21); // SRC_ENDIAN = 0x0: Little endian type at source
param->ccr = DMA4_CCR_SYNCHRO_CONTROL(omap3->dma_rreq) // Synchro control bits
| (1 << 5) // FS = 1: Packet mode with BS = 0x1
| (0 << 6) // READ_PRIORITY = 0x0: Low priority on read side
| (0 << 7) // ENABLE = 0x0: The logical channel is disabled.
| (0 << 8) // DMA4_CCRi[8] SUSPEND_SENSITIVE = 0
| (0 << 12) // DMA4_CCRi[13:12] SRC_AMODE = 0x0: Constant address mode
| (1 << 14) // DMA4_CCRi[15:14] DST_AMODE = 0x1: Post-incremented address mode
| (1 << 18) // DMA4_CCRi[18] BS = 0x1: Packet mode with FS = 0x1
| (1 << 24) // DMA4_CCRi[24] SEL_SRC_DST_SYNC = 0x1: Transfer is triggered by the source. The packet element number is specified in the DMA4_CSFI register.
| (0 << 25); // DMA4_CCRi[25] BUFFERING_DISABLE = 0x0
param->cssa = omap3->mmc_pbase + OMAP3_MMCHS_DATA;
param->cdsa = paddr;
param->csf = omap3->blksz >> 2;
} else {
static int omap_setup_dma( SIM_HBA *hba, paddr_t paddr, int len, int dir )
{
SIM_MMC_EXT *ext;
omap_ext_t *oext;
uintptr_t cbase;
ext = (SIM_MMC_EXT *)hba->ext;
oext = (omap_ext_t *)ext->handle;
if( oext->adma ) {
return( omap_setup_sgdma( hba, 0 ) );
}
cbase = oext->sdma_cbase;
if( ( len = omap_setup_pio( hba, len, dir ) ) ) {
out32( cbase + DMA4_CSR, 0x1FFE ); // Clear all status bits
out32( cbase + DMA4_CEN, len >> 2 );
out32( cbase + DMA4_CFN, 1 ); // Number of frames
out32( cbase + DMA4_CSE, 1 );
out32( cbase + DMA4_CDE, 1 );
out32( cbase + DMA4_CICR, 0 ); // We don't want any interrupts
if( dir == MMC_DIR_IN ) {
// setup receive SDMA channel
out32( cbase + DMA4_CSDP, (2 << 0) // DATA_TYPE = 0x2: 32 bit element
| (0 << 2) // RD_ADD_TRSLT = 0: Not used
| (0 << 6) // SRC_PACKED = 0x0: Cannot pack source data
| (0 << 7) // SRC_BURST_EN = 0x0: Cannot burst source
| (0 << 9) // WR_ADD_TRSLT = 0: Undefined
| (0 << 13) // DST_PACKED = 0x0: No packing
| (3 << 14) // DST_BURST_EN = 0x3: Burst at 16x32 bits
| (1 << 16) // WRITE_MODE = 0x1: Write posted
| (0 << 18) // DST_ENDIAN_LOCK = 0x0: Endianness adapt
| (0 << 19) // DST_ENDIAN = 0x0: Little Endian type at destination
| (0 << 20) // SRC_ENDIAN_LOCK = 0x0: Endianness adapt
| (0 << 21) ); // SRC_ENDIAN = 0x0: Little endian type at source
out32( cbase + DMA4_CCR, DMA4_CCR_SYNCHRO_CONTROL( oext->sdma_rreq ) // Synchro control bits
| (1 << 5) // FS = 1: Packet mode with BS = 0x1
| (0 << 6) // READ_PRIORITY = 0x0: Low priority on read side
| (0 << 7) // ENABLE = 0x0: The logical channel is disabled.
| (0 << 8) // DMA4_CCRi[8] SUSPEND_SENSITIVE = 0
| (0 << 12) // DMA4_CCRi[13:12] SRC_AMODE = 0x0: Constant address mode
| (1 << 14) // DMA4_CCRi[15:14] DST_AMODE = 0x1: Post-incremented address mode
| (1 << 18) // DMA4_CCRi[18] BS = 0x1: Packet mode with FS = 0x1
| (1 << 24) // DMA4_CCRi[24] SEL_SRC_DST_SYNC = 0x1: Transfer is triggered by the source. The packet element number is specified in the DMA4_CSFI register.
| (0 << 25) ); // DMA4_CCRi[25] BUFFERING_DISABLE = 0x0
out32( cbase + DMA4_CSSA, oext->mmc_pbase + OMAP_MMCHS_DATA );
out32( cbase + DMA4_CDSA, paddr );
out32( cbase + DMA4_CSF, oext->blksz >> 2 );
}
