/*!
\brief check DMA flag and interrupt enable bit is set or not
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to get flag
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] flag: specify get which flag
only one parameter can be selected which is shown as below:
\arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
\arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
\arg DMA_INT_FLAG_ERR: error interrupt flag of channel
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
{
uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
switch(flag){
case DMA_INT_FLAG_FTF:
interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE;
break;
case DMA_INT_FLAG_HTF:
interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE;
break;
case DMA_INT_FLAG_ERR:
interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE;
break;
default:
DMA_WRONG_HANDLE
}
if(interrupt_flag && interrupt_enable){
return SET;
}else{
return RESET;
}
}
/*!
\brief configure memory address generation generation_algorithm
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
\arg DMA_CHx(x=0..7)
\param[in] generation_algorithm: the address generation algorithm
\arg DMA_MEMORY_INCREASE_ENABLE: next address of memory is increasing address mode
\arg DMA_MEMORY_INCREASE_DISABLE: next address of memory is fixed address mode
\param[out] none
\retval none
*/
void dma_memory_address_generation_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t generation_algorithm)
{
if(DMA_MEMORY_INCREASE_ENABLE == generation_algorithm){
DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MNAGA;
}else{
DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MNAGA;
}
}
/*!
\brief configure the direction of data transfer on the channel
\param[in] channelx: specify which DMA channel
\arg DMA_CHx(x=0..6)
\param[in] direction: specify the direction of data transfer
\arg DMA_PERIPHERA_TO_MEMORY: read from peripheral and write to memory
\arg DMA_MEMORY_TO_PERIPHERA: read from memory and write to peripheral
\param[out] none
\retval none
*/
void dma_transfer_direction_config(dma_channel_enum channelx,uint8_t direction)
{
if(DMA_PERIPHERA_TO_MEMORY == direction){
DMA_CHCTL(channelx) &= ~DMA_CHXCTL_TM;
} else {
DMA_CHCTL(channelx) |= DMA_CHXCTL_TM;
}
}
/*!
\brief DMA flow controller configure
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
\arg DMA_CHx(x=0..7)
\param[in] controller: specify DMA flow controler
\arg DMA_FLOW_CONTROLLER_DMA: DMA is the flow controller
\arg DMA_FLOW_CONTROLLER_PERI: peripheral is the flow controller
\param[out] none
\retval none
*/
void dma_flow_controller_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t controller)
{
if(DMA_FLOW_CONTROLLER_DMA == controller){
DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_TFCS;
}else{
DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_TFCS;
}
}
/*!
\brief configure transfer data size of memory
\param[in] channelx: specify which DMA channel
\arg DMA_CHx(x=0..6)
\param[in] msize: transfer data size of memory
\arg DMA_MEMORY_WIDTH_8BIT: transfer data size of memory is 8-bit
\arg DMA_MEMORY_WIDTH_16BIT: transfer data size of memory is 16-bit
\arg DMA_MEMORY_WIDTH_32BIT: transfer data size of memory is 32-bit
\param[out] none
\retval none
*/
void dma_memory_width_config (dma_channel_enum channelx,uint32_t msize)
{
uint32_t ctl;
/* acquire DMA_CHxCTL register */
ctl = DMA_CHCTL(channelx);
/* assign regiser */
ctl &= ~DMA_CHXCTL_MWIDTH;
ctl |= msize;
DMA_CHCTL(channelx) = ctl;
}
/*!
\brief configure priority level of DMA channel
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
\arg DMA_CHx(x=0..7)
\param[in] priority: priority Level of this channel
\arg DMA_PRIORITY_LOW: low priority
\arg DMA_PRIORITY_MEDIUM: medium priority
\arg DMA_PRIORITY_HIGH: high priority
\arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority
\param[out] none
\retval none
*/
void dma_priority_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t priority)
{
uint32_t ctl;
/* acquire DMA_CHxCTL register */
ctl = DMA_CHCTL(dma_periph,channelx);
/* assign regiser */
ctl &= ~DMA_CHXCTL_PRIO;
ctl |= priority;
DMA_CHCTL(dma_periph,channelx) = ctl;
}
/*!
\brief configure transfer burst beats of peripheral
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
\arg DMA_CHx(x=0..7)
\param[in] pbeat: transfer burst beats
\arg DMA_PERIPH_BURST_SINGLE: peripheral transfer single burst
\arg DMA_PERIPH_BURST_4_BEAT: peripheral transfer 4-beat burst
\arg DMA_PERIPH_BURST_8_BEAT: peripheral transfer 8-beat burst
\arg DMA_PERIPH_BURST_16_BEAT: peripheral transfer 16-beat burst
\param[out] none
\retval none
*/
void dma_periph_burst_beats_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t pbeat)
{
uint32_t ctl;
/* acquire DMA_CHxCTL register */
ctl = DMA_CHCTL(dma_periph,channelx);
/* assign regiser */
ctl &= ~DMA_CHXCTL_PBURST;
ctl |= pbeat;
DMA_CHCTL(dma_periph,channelx) = ctl;
}
/*!
\brief configure transfer data size of peripheral
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
\arg DMA_CHx(x=0..7)
\param[in] msize: transfer data size of peripheral
\arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data size of peripheral is 8-bit
\arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data size of peripheral is 16-bit
\arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data size of peripheral is 32-bit
\param[out] none
\retval none
*/
void dma_periph_width_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t psize)
{
uint32_t ctl;
/* acquire DMA_CHxCTL register */
ctl = DMA_CHCTL(dma_periph,channelx);
/* assign regiser */
ctl &= ~DMA_CHXCTL_PWIDTH;
ctl |= psize;
DMA_CHCTL(dma_periph,channelx) = ctl;
}
/*!
\brief DMA switch buffer mode enable
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
\arg DMA_CHx(x=0..7)
\param[in] newvalue: ENABLE or DISABLE
\param[out] none
\retval none
*/
void dma_switch_buffer_mode_enable(uint32_t dma_periph,dma_channel_enum channelx,ControlStatus newvalue)
{
if(ENABLE == newvalue){
/* switch buffer mode enable */
DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_SBMEN;
}else{
/* switch buffer mode disable */
DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_SBMEN;
}
}
/*!
\brief deinitialize DMA a channel registers
\param[in] channelx: specify which DMA channel is deinitialized
\arg DMA_CHx(x=0..6)
\param[out] none
\retval none
*/
void dma_deinit(dma_channel_enum channelx)
{
/* disable DMA a channel */
DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN;
/* reset DMA channel registers */
DMA_CHCTL(channelx) = DMA_CHCTL_RESET_VALUE;
DMA_CHCNT(channelx) = DMA_CHCNT_RESET_VALUE;
DMA_CHPADDR(channelx) = DMA_CHPADDR_RESET_VALUE;
DMA_CHMADDR(channelx) = DMA_CHMADDR_RESET_VALUE;
DMA_INTC |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE,channelx);
}
/*!
\brief DMA channel peripheral select
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
\arg DMA_CHx(x=0..7)
\param[in] sub_periph: specify DMA channel peripheral
\arg DMA_SUBPERIx(x=0..7)
\param[out] none
\retval none
*/
void dma_channel_subperipheral_select(uint32_t dma_periph,dma_channel_enum channelx,dma_subperipheral_enum sub_periph)
{
uint32_t ctl;
/* acquire DMA_CHxCTL register */
ctl = DMA_CHCTL(dma_periph,channelx);
/* assign regiser */
ctl &= ~DMA_CHXCTL_PERIEN;
ctl |= ((uint32_t)sub_periph << CHXCTL_PERIEN_OFFSET);
DMA_CHCTL(dma_periph,channelx) = ctl;
}
/*!
\brief configure the direction of data transfer on the channel
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
\arg DMA_CHx(x=0..7)
\param[in] direction: specify the direction of data transfer
\arg DMA_PERIPH_TO_MEMORY: read from peripheral and write to memory
\arg DMA_MEMORY_TO_PERIPH: read from memory and write to peripheral
\arg DMA_MEMORY_TO_MEMORY: read from memory and write to memory
\param[out] none
\retval none
*/
void dma_transfer_direction_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t direction)
{
uint32_t ctl;
/* acquire DMA_CHxCTL register */
ctl = DMA_CHCTL(dma_periph,channelx);
/* assign regiser */
ctl &= ~DMA_CHXCTL_TM;
ctl |= direction;
DMA_CHCTL(dma_periph,channelx) = ctl;
}
/*!
\brief DMA switch buffer mode config
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
\arg DMA_CHx(x=0..7)
\param[in] memory1_addr: memory1 base address
\param[in] memory_select: DMA_MEMORY_0 or DMA_MEMORY_1
\param[out] none
\retval none
*/
void dma_switch_buffer_mode_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t memory1_addr,uint32_t memory_select)
{
/* configure memory1 base address */
DMA_CHM1ADDR(dma_periph,channelx) = memory1_addr;
if(DMA_MEMORY_0 == memory_select){
DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MBS;
}else{
DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MBS;
}
}
/*!
\brief configure peripheral address generation generation_algorithm
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
\arg DMA_CHx(x=0..7)
\param[in] generation_algorithm: the address generation algorithm
\arg DMA_PERIPH_INCREASE_ENABLE: next address of peripheral is increasing address mode
\arg DMA_PERIPH_INCREASE_DISABLE: next address of peripheral is fixed address mode
\arg DMA_PERIPH_INCREASE_FIX: increasing steps of peripheral address is fixed
\param[out] none
\retval none
*/
void dma_peripheral_address_generation_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t generation_algorithm)
{
if(DMA_PERIPH_INCREASE_ENABLE == generation_algorithm){
DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA;
}else if(DMA_PERIPH_INCREASE_DISABLE == generation_algorithm){
DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_PNAGA;
}else{
DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA;
DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PAIF;
}
}
/*!
\brief configure the direction of data transfer on the channel
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] direction: specify the direction of data transfer
\arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory
\arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral
\param[out] none
\retval none
*/
void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
if(DMA_PERIPHERAL_TO_MEMORY == direction){
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
} else {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
}
}
/*!
\brief deinitialize DMA a channel registers
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel is deinitialized
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
/* disable DMA a channel */
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN;
/* reset DMA channel registers */
DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE;
DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE;
DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE;
DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE;
DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx);
}
/*!
\brief configure transfer data size of peripheral
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] pwidth: transfer data width of peripheral
\arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit
\arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit
\arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit
\param[out] none
\retval none
*/
void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth)
{
uint32_t ctl;
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
/* acquire DMA_CHxCTL register */
ctl = DMA_CHCTL(dma_periph, channelx);
/* assign regiser */
ctl &= ~DMA_CHXCTL_PWIDTH;
ctl |= pwidth;
DMA_CHCTL(dma_periph, channelx) = ctl;
}
/*!
\brief disable DMA interrupt
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
\arg DMA_CHx(x=0..7)
\param[in] source: specify which interrupt to disbale
\arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable
\arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable
\arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable
\arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable
\arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable
\param[out] none
\retval none
*/
void dma_interrupt_disable(uint32_t dma_periph,dma_channel_enum channelx,uint32_t source)
{
if(DMA_CHXFCTL_FEEIE != source){
DMA_CHCTL(dma_periph,channelx) &= ~source;
}else{
DMA_CHFCTL(dma_periph,channelx) &= ~source;
}
}
/*!
\brief DMA using memory get
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
\arg DMA_CHx(x=0..7)
\param[out] none
\retval the using memory
*/
uint32_t dma_using_memory_get(uint32_t dma_periph,dma_channel_enum channelx)
{
if((DMA_CHCTL(dma_periph,channelx)) & DMA_CHXCTL_MBS){
return DMA_MEMORY_1;
}else{
return DMA_MEMORY_0;
}
}
/*!
\brief disable DMA circulation mode
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN;
}
/*!
\brief disable DMA interrupt
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] source: specify which interrupt to disbale
one or more parameters can be selected which are shown as below
\arg DMA_INT_FTF: channel full transfer finish interrupt
\arg DMA_INT_HTF: channel half transfer finish interrupt
\arg DMA_INT_ERR: channel error interrupt
\param[out] none
\retval none
*/
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) &= ~source;
}
/*!
\brief deinitialize DMA a channel registers
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel is deinitialized
\arg DMA_CHx(x=0..7)
\param[out] none
\retval none
*/
void dma_deinit(uint32_t dma_periph,dma_channel_enum channelx)
{
/* disable DMA a channel */
DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CHEN;
/* reset DMA channel registers */
DMA_CHCTL(dma_periph,channelx) = DMA_CHCTL_RESET_VALUE;
DMA_CHCNT(dma_periph,channelx) = DMA_CHCNT_RESET_VALUE;
DMA_CHPADDR(dma_periph,channelx) = DMA_CHPADDR_RESET_VALUE;
DMA_CHM0ADDR(dma_periph,channelx) = DMA_CHMADDR_RESET_VALUE;
DMA_CHM1ADDR(dma_periph,channelx) = DMA_CHMADDR_RESET_VALUE;
DMA_CHFCTL(dma_periph,channelx) = DMA_CHFCTL_RESET_VALUE;
if(channelx < DMA_CH4){
DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE,channelx);
}else{
DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE,channelx);
}
}
/*!
\brief disable next address increasement algorithm of peripheral
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
}
/*!
\brief disable memory to memory mode
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M;
}
/*!
\brief enable DMA channel
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN;
}
/*!
\brief enable next address increasement algorithm of memory
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
}
/*!
\brief initialize DMA single data mode
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel is initialized
\arg DMA_CHx(x=0..7)
\param[in] init_struct: the data needed to initialize DMA single data mode
periph_addr: peripheral base address
periph_memory_width: DMA_PERIPH_WIDTH_8BIT,DMA_PERIPH_WIDTH_16BIT,DMA_PERIPH_WIDTH_32BIT
periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE,DMA_PERIPH_INCREASE_FIX
memory0_addr: memory base address
memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE
direction: DMA_PERIPH_TO_MEMORY,DMA_MEMORY_TO_PERIPH,DMA_MEMORY_TO_MEMORY
number: the number of remaining data to be transferred by the DMA
priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH
circular_mode: DMA_CIRCULAR_MODE_ENABLE,DMA_CIRCULAR_MODE_DISABLE
\param[out] none
\retval none
*/
void dma_single_data_mode_init(uint32_t dma_periph,dma_channel_enum channelx,dma_single_data_parameter_struct init_struct)
{
uint32_t ctl;
/* select single data mode */
DMA_CHFCTL(dma_periph,channelx) &= ~DMA_CHXFCTL_MDMEN;
/* configure peripheral base address */
DMA_CHPADDR(dma_periph,channelx) = init_struct.periph_addr;
/* configure memory base address */
DMA_CHM0ADDR(dma_periph,channelx) = init_struct.memory0_addr;
/* configure the number of remaining data to be transferred */
DMA_CHCNT(dma_periph,channelx) = init_struct.number;
/* configure peripheral and memory transfer width,channel priotity,transfer mode */
ctl = DMA_CHCTL(dma_periph,channelx);
ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO | DMA_CHXCTL_TM);
ctl |= (init_struct.periph_memory_width | (init_struct.periph_memory_width << 2) | init_struct.priority | init_struct.direction);
DMA_CHCTL(dma_periph,channelx) = ctl;
/* configure peripheral increasing mode */
if(DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc){
DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA;
}else if(DMA_PERIPH_INCREASE_DISABLE == init_struct.periph_inc){
DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_PNAGA;
}else{
DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PAIF;
}
/* configure memory increasing mode */
if(DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc){
DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MNAGA;
}else{
DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MNAGA;
}
/* configure DMA circular mode */
if(DMA_CIRCULAR_MODE_ENABLE == init_struct.circular_mode){
DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CMEN;
}else{
DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CMEN;
}
}
/*!
\brief initialize DMA channel
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel is initialized
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] init_struct: the data needed to initialize DMA channel
periph_addr: peripheral base address
periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT
periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE
memory_addr: memory base address
memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT
memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE
direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL
number: the number of remaining data to be transferred by the DMA
priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH
\param[out] none
\retval none
*/
void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct init_struct)
{
uint32_t ctl;
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
/* configure peripheral base address */
DMA_CHPADDR(dma_periph, channelx) = init_struct.periph_addr;
/* configure memory base address */
DMA_CHMADDR(dma_periph, channelx) = init_struct.memory_addr;
/* configure the number of remaining data to be transferred */
DMA_CHCNT(dma_periph, channelx) = (init_struct.number & DMA_CHANNEL_CNT_MASK);
/* configure peripheral transfer width,memory transfer width, */
ctl = DMA_CHCTL(dma_periph, channelx);
ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO);
ctl |= (init_struct.periph_width | init_struct.memory_width | init_struct.priority);
DMA_CHCTL(dma_periph, channelx) = ctl;
/* configure peripheral increasing mode */
if(DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc){
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
}else{
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
}
/* configure memory increasing mode */
if(DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc){
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
}else{
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
}
/* configure the direction of data transfer */
if(DMA_PERIPHERAL_TO_MEMORY == init_struct.direction){
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
}else{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
}
}
/*!
\brief disable DMA channel
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
\arg DMA_CHx(x=0..7)
\param[out] none
\retval none
*/
void dma_channel_disable(uint32_t dma_periph,dma_channel_enum channelx)
{
DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CHEN;
}
/*!
\brief enable DMA circulation mode
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
\arg DMA_CHx(x=0..7)
\param[out] none
\retval none
*/
void dma_circulation_enable(uint32_t dma_periph,dma_channel_enum channelx)
{
DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CMEN;
}
