/**
* Called at the end of each DMA transaction. Refresh the flag indicating which
* DMA buffer to write new data from the PIOS_COM fifo into the buffer
*/
void PIOS_OVERO_DMA_irq_handler(uint32_t overo_id)
{
struct pios_overo_dev *overo_dev = (struct pios_overo_dev *)overo_id;
if (!PIOS_OVERO_validate(overo_dev)) {
return;
}
DMA_ClearFlag(overo_dev->cfg->dma.tx.channel, overo_dev->cfg->dma.irq.flags);
overo_dev->writing_buffer = 1 - DMA_GetCurrentMemoryTarget(overo_dev->cfg->dma.tx.channel);
overo_dev->writing_offset = 0;
/* bool rx_need_yield;
// Get data from the Rx buffer and add to the fifo
(void) (overo_dev->rx_in_cb)(overo_dev->rx_in_context,
&overo_dev->rx_buffer[overo_dev->writing_buffer][0],
PACKET_SIZE, NULL, &rx_need_yield);
if(rx_need_yield) {
vPortYieldFromISR();
}
// Fill the buffer with known value to prevent rereading these bytes
memset(&overo_dev->rx_buffer[overo_dev->writing_buffer][0], 0xFF, PACKET_SIZE);
*/
// Fill the buffer with known value to prevent resending any bytes
memset(&overo_dev->tx_buffer[overo_dev->writing_buffer][0], 0xFF, PACKET_SIZE);
// Load any pending bytes from TX fifo
PIOS_OVERO_WriteData(overo_dev);
overo_dev->packets++;
}
/**
* @brief Interrupt handler of DCMI DMA stream
*/
void DMA2_Stream1_IRQHandler(void)
{
/* transfer completed */
if (DMA_GetITStatus(DMA2_Stream1, DMA_IT_TCIF1) != RESET)
{
DMA_ClearITPendingBit(DMA2_Stream1, DMA_IT_TCIF1);
frame_counter++;
if(global_data.param[PARAM_VIDEO_ONLY])
{
if (frame_counter >= 4)
{
dcmi_dma_disable();
calibration_used = DMA_GetCurrentMemoryTarget(DMA2_Stream1);
calibration_unused = dcmi_image_buffer_unused;
calibration_mem0 = dcmi_image_buffer_memory0;
calibration_mem1 = dcmi_image_buffer_memory1;
}
}
return;
}
/* transfer half completed
*
* We use three buffers and switch the buffers if dma transfer
* is in half state.
*/
if (DMA_GetITStatus(DMA2_Stream1, DMA_IT_HTIF1) != RESET)
{
DMA_ClearITPendingBit(DMA2_Stream1, DMA_IT_HTIF1);
}
dma_swap_buffers();
}
void DMA2_Stream0_IRQHandler(void) {
if (DMA_GetITStatus(DMA2_Stream0, DMA_IT_TCIF0) != RESET) {
if (fdi_adc_callback) {
volatile uint16_t *buffer = (DMA_GetCurrentMemoryTarget(DMA2_Stream0) == 0) ? fdi_adc_dma_buffer_1 : fdi_adc_dma_buffer_0;
(*fdi_adc_callback)(buffer, fdi_adc_dma_buffer_length);
}
DMA_ClearITPendingBit(DMA2_Stream0, DMA_IT_TCIF0);
}
}
void DMA1_Stream0_IRQHandler(void)
{
uint8_t Key_Down;
//Check to see which set of buffers are currently in use
DMA_RX_Memory = DMA_GetCurrentMemoryTarget(DMA1_Stream0 );
DMA_TX_Memory = DMA_GetCurrentMemoryTarget(DMA1_Stream5 );
if (Tx_Flag == 0) {
Rcvr_DSP();
}
else {
switch (Mode_GetCurrentMode()) {
case MODE_SSB:
Xmit_SSB();
break;
case MODE_CW:
Key_Down = GPIO_ReadInputDataBit(GPIOC, GPIO_Pin_9 );
if (Key_Down == 0)
key = Amp0;
else
key = 0.0;
Xmit_CW();
break;
case MODE_PSK:
Xmit_PSK();
break;
} //End of Mode Switch
}
DSP_Flag = 1;
//Clear the DMA buffer full interrupt flag
DMA_ClearITPendingBit(DMA1_Stream0, DMA_IT_TCIF0 );
}
/**
* @brief Swap DMA image buffer addresses
*/
void dma_swap_buffers(void)
{
/* check which buffer is in use */
if (DMA_GetCurrentMemoryTarget(DMA2_Stream1))
{
/* swap dcmi image buffer */
if (dcmi_image_buffer_unused == 1)
DMA_MemoryTargetConfig(DMA2_Stream1, (uint32_t) dcmi_image_buffer_8bit_1, DMA_Memory_0);
else if (dcmi_image_buffer_unused == 2)
DMA_MemoryTargetConfig(DMA2_Stream1, (uint32_t) dcmi_image_buffer_8bit_2, DMA_Memory_0);
else
DMA_MemoryTargetConfig(DMA2_Stream1, (uint32_t) dcmi_image_buffer_8bit_3, DMA_Memory_0);
int tmp_buffer = dcmi_image_buffer_memory0;
dcmi_image_buffer_memory0 = dcmi_image_buffer_unused;
dcmi_image_buffer_unused = tmp_buffer;
}
else
{
/* swap dcmi image buffer */
if (dcmi_image_buffer_unused == 1)
DMA_MemoryTargetConfig(DMA2_Stream1, (uint32_t) dcmi_image_buffer_8bit_1, DMA_Memory_1);
else if (dcmi_image_buffer_unused == 2)
DMA_MemoryTargetConfig(DMA2_Stream1, (uint32_t) dcmi_image_buffer_8bit_2, DMA_Memory_1);
else
DMA_MemoryTargetConfig(DMA2_Stream1, (uint32_t) dcmi_image_buffer_8bit_3, DMA_Memory_1);
int tmp_buffer = dcmi_image_buffer_memory1;
dcmi_image_buffer_memory1 = dcmi_image_buffer_unused;
dcmi_image_buffer_unused = tmp_buffer;
}
/* set next time_between_images */
cycle_time = get_boot_time_us() - time_last_frame;
time_last_frame = get_boot_time_us();
if(image_counter) // image was not fetched jet
{
time_between_next_images = time_between_next_images + cycle_time;
}
else
{
time_between_next_images = cycle_time;
}
/* set new image true and increment frame counter*/
image_counter += 1;
return;
}
void DMA1_Stream0_IRQHandler(void)
{
static uint16_t msg_id[2] = {0,0};
static int wrr = 0;
static int msg_index = 0;
static uint16_t data_temp[2] = {0,0};
static uint32_t mode = DLE_STX;
uint32_t *pdata = (uint32_t*)&data_temp[0];
uint16_t *padpcm_msg;
uint32_t* pin;
uint32_t* pout;
uint32_t crc;
int i,j,id,adr;
DMA_ClearFlag(DMA1_Stream0, DMA_IT_TC | DMA_IT_TE);
DMA_ClearITPendingBit(DMA1_Stream0, DMA_IT_TCIF0 | DMA_IT_TEIF0);
id = DMA_GetCurrentMemoryTarget(DMA1_Stream0);
for(i = 0; i < SPI_RX_DMA; i++)
{
data_temp[1] = data_temp[0];
data_temp[0] = spi_dma_buffer[id][i];
if(mode == DLE_STX)
{
if(*pdata == DLE_STX)
{
mode = DLE_ETX;
padpcm_msg = (uint16_t*)&adpcm_msg[msg_index];
wrr = 0;
}
}
else if(mode == DLE_ETX)
{
if(*pdata == DLE_ETX)
{
CRC_ResetDR();
crc = CRC_CalcBlockCRC(((uint32_t*)&adpcm_msg[msg_index])+1,msg_32bit_size-1);
if(crc == adpcm_msg[msg_index].crc)
{
if(adpcm_msg[msg_index].msg_id == F415_CHECK_SPI_CONNECT+100)
{
t_info.f415_spi1_error = 0;
t_info.f415_mode = F415_STOP_MODE;
}
else if(adpcm_msg[msg_index].msg_id == F415_AUDIO_STREAM)
{
t_info.f415_mode = F415_AUDIO_STREAM_MODE;
for(i = 0; i < MAX_CHANNEL; i++)
{
id = adpcm_ctrl[i].id;
adr = adpcm_ctrl[i].adr++;
pin = (uint32_t*)&padpcm[id][i]->adpcm_data[adr][0];
pout = (uint32_t*)&adpcm_msg[msg_index].adpcm_block[i].adpcm_data[0];
for(j = 0; j < 28; j++) *(pin++) = *(pout++);
if(adr == 0)
{
padpcm[id][i]->prevsample = adpcm_msg[msg_index].adpcm_block[i].prevsample;
padpcm[id][i]->previndex = adpcm_msg[msg_index].adpcm_block[i].previndex;
padpcm[id][i]->channel_id = i;
padpcm[id][i]->time = GetTime();
adpcm_ctrl[i].crc = crc32_t(-1,padpcm[id][i],116,116);
}
else if(adr == (ADPCM_MAX_BLOCK-1))
{
padpcm[id][i]->crc = crc32_t(adpcm_ctrl[i].crc,&padpcm[id][i]->adpcm_data[adr][0],120,120) ^ 0xffffffff;
adpcm_ctrl[i].id ^= 1;
adpcm_ctrl[i].adr = 0;
adpcm_ctrl[i].done = 1;
}
else
{
adpcm_ctrl[i].crc = crc32_t(adpcm_ctrl[i].crc,&padpcm[id][i]->adpcm_data[adr][0],112,112);
}
}
if(adr == (ADPCM_MAX_BLOCK-1))
{
for(i = 0; i < MAX_CHANNEL; i++) adpcm_ready |= adpcm_ctrl[i].done;
}
}
}
msg_id[0] = adpcm_msg[msg_index].msg_counter;
if(msg_id[0] != (msg_id[1]+1))
{
//sys_info.L151_stream_error++;
t_info.crc_binar_error++;
}
msg_id[1] = msg_id[0];
*pdata = 0;
mode = DLE_STX;
msg_index ^= 1;
}
else if(*pdata == DLE_DLE)
{
data_temp[0] = 0;
}
else
{
if(wrr++ < msg_16bit_size) *(padpcm_msg++) = data_temp[0];
}
}
}
}
