/* ===================================================================*/
LDD_TDeviceData* DMA1_Init(void)
{
DMA1_TDeviceData *DevDataPtr; /* LDD device structure */
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DevDataPtr = &DevDataPtr__DEFAULT_RTOS_ALLOC;
/* {Default RTOS Adapter} Driver memory allocation: Fill the allocated memory by zero value */
PE_FillMemory(DevDataPtr, 0U, sizeof(DMA1_TDeviceData));
/* Transfer complete interrupt vector(INT_DMA0) allocation */
/* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_DMA0__DEFAULT_RTOS_ISRPARAM = DevDataPtr;
/* Transfer error interrupt vector(INT_DMA_Error) allocation */
/* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_DMA_Error__DEFAULT_RTOS_ISRPARAM = DevDataPtr;
/* Transfer complete interrupt vector(INT_DMA0) priority setting */
/* NVIC_IPR0: PRI_0=1 */
NVIC_IPR0 = (uint32_t)((NVIC_IPR0 & (uint32_t)~(uint32_t)(
NVIC_IP_PRI_0(0x02)
)) | (uint32_t)(
NVIC_IP_PRI_0(0x01)
));
/* NVIC_ISER: SETENA31=0,SETENA30=0,SETENA29=0,SETENA28=0,SETENA27=0,SETENA26=0,SETENA25=0,SETENA24=0,SETENA23=0,SETENA22=0,SETENA21=0,SETENA20=0,SETENA19=0,SETENA18=0,SETENA17=0,SETENA16=0,SETENA15=0,SETENA14=0,SETENA13=0,SETENA12=0,SETENA11=0,SETENA10=0,SETENA9=0,SETENA8=0,SETENA7=0,SETENA6=0,SETENA5=0,SETENA4=0,SETENA3=0,SETENA2=0,SETENA1=0,SETENA0=1 */
NVIC_ISER = NVIC_ISER_SETENA0_MASK;
/* NVIC_ICER: CLRENA31=0,CLRENA30=0,CLRENA29=0,CLRENA28=0,CLRENA27=0,CLRENA26=0,CLRENA25=0,CLRENA24=0,CLRENA23=0,CLRENA22=0,CLRENA21=0,CLRENA20=0,CLRENA19=0,CLRENA18=0,CLRENA17=0,CLRENA16=0,CLRENA15=0,CLRENA14=0,CLRENA13=0,CLRENA12=0,CLRENA11=0,CLRENA10=0,CLRENA9=0,CLRENA8=0,CLRENA7=0,CLRENA6=0,CLRENA5=0,CLRENA4=0,CLRENA3=0,CLRENA2=0,CLRENA1=0,CLRENA0=0 */
NVIC_ICER = 0x00U;
/* Transfer error interrupt vector(INT_DMA_Error) priority setting */
/* NVIC_IPR1: PRI_4=1 */
NVIC_IPR1 = (uint32_t)((NVIC_IPR1 & (uint32_t)~(uint32_t)(
NVIC_IP_PRI_4(0x02)
)) | (uint32_t)(
NVIC_IP_PRI_4(0x01)
));
/* NVIC_ISER: SETENA31=0,SETENA30=0,SETENA29=0,SETENA28=0,SETENA27=0,SETENA26=0,SETENA25=0,SETENA24=0,SETENA23=0,SETENA22=0,SETENA21=0,SETENA20=0,SETENA19=0,SETENA18=0,SETENA17=0,SETENA16=0,SETENA15=0,SETENA14=0,SETENA13=0,SETENA12=0,SETENA11=0,SETENA10=0,SETENA9=0,SETENA8=0,SETENA7=0,SETENA6=0,SETENA5=0,SETENA4=1,SETENA3=0,SETENA2=0,SETENA1=0,SETENA0=0 */
NVIC_ISER = NVIC_ISER_SETENA4_MASK;
/* NVIC_ICER: CLRENA31=0,CLRENA30=0,CLRENA29=0,CLRENA28=0,CLRENA27=0,CLRENA26=0,CLRENA25=0,CLRENA24=0,CLRENA23=0,CLRENA22=0,CLRENA21=0,CLRENA20=0,CLRENA19=0,CLRENA18=0,CLRENA17=0,CLRENA16=0,CLRENA15=0,CLRENA14=0,CLRENA13=0,CLRENA12=0,CLRENA11=0,CLRENA10=0,CLRENA9=0,CLRENA8=0,CLRENA7=0,CLRENA6=0,CLRENA5=0,CLRENA4=0,CLRENA3=0,CLRENA2=0,CLRENA1=0,CLRENA0=0 */
NVIC_ICER = 0x00U;
/* Enable clock gates */
#ifdef SIM_PDD_CLOCK_GATE_DMA
SIM_PDD_SetClockGate(SIM_BASE_PTR, SIM_PDD_CLOCK_GATE_DMA, PDD_ENABLE);
#endif
#ifdef SIM_PDD_CLOCK_GATE_DMAMUX
SIM_PDD_SetClockGate(SIM_BASE_PTR, SIM_PDD_CLOCK_GATE_DMAMUX, PDD_ENABLE);
#endif
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_DMA1_ID,DevDataPtr);
/* Discard previous setting */
DMA_PDD_ClearRequestEnable(DMA_BASE_PTR, DMA_PDD_ALL_CHANNELS, 0x00U); /* Disable all request from peripheral */
DMA_PDD_ClearErrorInterruptEnable(DMA_BASE_PTR, DMA_PDD_ALL_CHANNELS, 0x00U); /* Disable all error interrupts */
DMA_PDD_CancelTransfer(DMA_BASE_PTR); /* Cancel transfer (if any in progress) */
DMA_PDD_ClearInterruptFlags(DMA_BASE_PTR, DMA_PDD_ALL_CHANNELS, 0x00U); /* Clear all channel interrupt flags */
DMA_PDD_InitChannelsPriority(DMA_BASE_PTR,DMA1_DevConst.ChnPriorities); /* Initialize channel TCD (channel registers) */
DMA_CR = 0x00U; /* initialize Control register */
return DevDataPtr;
}
/* ===================================================================*/
LDD_TDeviceData* DMA1_Init(LDD_TUserData *UserDataPtr)
{
uint8_t i;
DMA1_TDeviceData *DeviceDataPtr; /* LDD device structure */
DMA1_TDescriptorRecord *DescriptorRecordPtr; /* Auxiliary local pointer to internal descriptor records. */
/* Allocate HAL device structure */
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPtr = &DeviceDataPtr__DEFAULT_RTOS_ALLOC;
DeviceDataPtr->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
/* Enable device clock gate */
/* SIM_SCGC7: DMA=1 */
SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;
/* SIM_SCGC6: DMAMUX=1 */
SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
/* Transfer compete interrupt vector(s) allocation */
/* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_DMA2__DEFAULT_RTOS_ISRPARAM = DeviceDataPtr;
/* Transfer compete interrupt vector(s) priority setting */
/* NVIC_IPR0: PRI_2=0x80 */
NVIC_IPR0 = (uint32_t)((NVIC_IPR0 & (uint32_t)~(uint32_t)(
NVIC_IP_PRI_2(0x7F)
)) | (uint32_t)(
NVIC_IP_PRI_2(0x80)
));
/* NVIC_ISER: SETENA|=4 */
NVIC_ISER |= NVIC_ISER_SETENA(0x04);
for (i = 0U; i < DMA1_DMA_CHANNELS_NUMBER; i++) {
DMA_PDD_WriteControlReg(DMA_BASE_PTR, i, 0U); /* Clear control register. Disable all interrupts and HW requests. */
DMA_PDD_ClearInterruptFlags(DMA_BASE_PTR, i, DMA_PDD_TRANSFER_COMPLETE_FLAG); /* Clear request interrupt flags */
}
/* Initialization of channels record field. */
memset(DeviceDataPtr->ChannelRecord, 0, DMA1_DMA_CHANNELS_NUMBER * sizeof(DeviceDataPtr->ChannelRecord[0]));
//for(i = 0U; i < DMA1_DMA_CHANNELS_NUMBER; i++) {
// DeviceDataPtr->ChannelRecord[i] = NULL; /* Clear pointer to descriptor record of all channels. */
//}
/* Initialization of channel and descriptor record fields. */
for(i = 0U; i < DMA1_CONFIGURED_CHANNELS_NUMBER; i++) {
DescriptorRecordPtr = &(DeviceDataPtr->DescriptorRecord[i]); /* Store local pointer to descriptor record. */
DescriptorRecordPtr->ChannelNumber = DMA1_ChannelNumbers[i]; /* Store associated channel number. */
DescriptorRecordPtr->DescriptorPtr = NULL; /* Set channel as free. */
DescriptorRecordPtr->Interrupts = DMA1_ChannelInterrupts[i]; /* Store associated channel interrupts enabled/disabled status. */
DescriptorRecordPtr->Initialized = FALSE; /* Set channel as not initialized. */
DescriptorRecordPtr->Enabled = FALSE; /* Set channel as disabled. */
DeviceDataPtr->ChannelRecord[DMA1_ChannelNumbers[i]] = DescriptorRecordPtr; /* Store pointers to descriptor records of fixed channels. */
DeviceDataPtr->EventMask[DMA1_ChannelNumbers[i]] = 0U; /* Clear channel event mask. */
}
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_DMA1_ID,DeviceDataPtr);
return ((LDD_TDeviceData *)DeviceDataPtr); /* Return pointer to the data structure */
}