void DMAInit(void) { DMA_disableTransferDuringReadModifyWrite(); DMA_initParam initParam = {0}; initParam.channelSelect = DMA_CHANNEL_0; initParam.transferModeSelect = DMA_TRANSFER_REPEATED_BLOCK; initParam.transferSize = 3; initParam.triggerSourceSelect = DMA_TRIGGERSOURCE_24; initParam.transferUnitSelect = DMA_SIZE_SRCWORD_DSTWORD; initParam.triggerTypeSelect = DMA_TRIGGER_RISINGEDGE; DMA_init(&initParam); DMA_setSrcAddress(DMA_CHANNEL_0, ADC12_A_getMemoryAddressForDMA(ADC12_A_BASE, ADC12_A_MEMORY_0), DMA_DIRECTION_INCREMENT); DMA_setDstAddress(DMA_CHANNEL_0, (uint32_t)&DMA_DST, DMA_DIRECTION_INCREMENT); //Enable DMA channel 0 interrupt DMA_clearInterrupt(DMA_CHANNEL_0); DMA_enableInterrupt(DMA_CHANNEL_0); //Enable transfers on DMA channel 0 DMA_enableTransfers(DMA_CHANNEL_0); }
void * memcpyDMA (void * dest, const void * source, size_t count) { if (count == 0){ //do nothing if zero bytes to transfer return (dest); } //DMA4 workaround - disable DMA transfers during read-modify-write CPU //operations #ifndef DRIVERLIB_LEGACY_MODE DMA_disableTransferDuringReadModifyWrite(); DMA_setSrcAddress(USB_DMA_CHAN, (uint32_t)source, DMA_DIRECTION_INCREMENT); DMA_setDstAddress(USB_DMA_CHAN, (uint32_t)dest, DMA_DIRECTION_INCREMENT); //DMA4 workaround - re-enable DMA transfers during read-modify-write CPU //operations DMA_enableTransferDuringReadModifyWrite(); DMA_setTransferSize(USB_DMA_CHAN, count); DMA_enableTransfers(USB_DMA_CHAN); DMA_startTransfer(USB_DMA_CHAN); while (DMA_getInterruptStatus(USB_DMA_CHAN) == DMA_INT_INACTIVE); DMA_disableTransfers(USB_DMA_CHAN); #else DMA_disableTransferDuringReadModifyWrite(DMA_BASE); DMA_setSrcAddress(DMA_BASE, USB_DMA_CHAN, (uint32_t)source, DMA_DIRECTION_INCREMENT); DMA_setDstAddress(DMA_BASE, USB_DMA_CHAN, (uint32_t)dest, DMA_DIRECTION_INCREMENT); //DMA4 workaround - re-enable DMA transfers during read-modify-write CPU //operations DMA_enableTransferDuringReadModifyWrite(DMA_BASE); DMA_setTransferSize(DMA_BASE, USB_DMA_CHAN, count); DMA_enableTransfers(DMA_BASE, USB_DMA_CHAN); DMA_startTransfer(DMA_BASE, USB_DMA_CHAN); while (DMA_getInterruptStatus(DMA_BASE, USB_DMA_CHAN) == DMA_INT_INACTIVE); DMA_disableTransfers(DMA_BASE, USB_DMA_CHAN); #endif return (dest); }
void main (void) { unsigned int ADC_Result[64]; volatile unsigned int ADC_Result_Average; unsigned char i; unsigned int ADC_Result_sum; //Stop Watchdog Timer WDT_hold(__MSP430_BASEADDRESS_WDT_A__); //Initialize the ADC10 Module /* * Base Address for the ADC10 Module * Use internal ADC10 bit as sample/hold signal to start conversion * USE MODOSC 5MHZ Digital Oscillator as clock source * Use default clock divider of 1 */ ADC10_init(__MSP430_BASEADDRESS_ADC10_A__, ADC10_SAMPLEHOLDSOURCE_SC, ADC10_CLOCKSOURCE_ADC10OSC, ADC10_CLOCKDIVIDER_1); ADC10_enable(__MSP430_BASEADDRESS_ADC10_A__); /* * Base Address for the ADC10 Module * Sample/hold for 16 clock cycles * Enable Multiple Sampling */ ADC10_setupSamplingTimer(__MSP430_BASEADDRESS_ADC10_A__, ADC10_CYCLEHOLD_16_CYCLES, ADC10_MULTIPLESAMPLESENABLE); //Configure Memory Buffer /* * Base Address for the ADC10 Module * Use input A1 * Use positive reference of AVcc * Use negative reference of AVss */ ADC10_memoryConfigure(__MSP430_BASEADDRESS_ADC10_A__, ADC10_INPUT_A1, ADC10_VREFPOS_AVCC, ADC10_VREFNEG_AVSS); //Initialize and Setup DMA Channel 0 /* * Base Address for the DMA Module * Configure DMA channel 0 * Configure channel for repeated single transfer * DMA interrupt flag will be set after every 64 transfers * Use DMA Trigger Source 24 (ADC10IFG) * Transfer Word-to-Word * Trigger upon Rising Edge of Trigger Source Signal */ DMA_init(__MSP430_BASEADDRESS_DMAX_3__, DMA_CHANNEL_0, DMA_TRANSFER_REPEATED_SINGLE, 64, DMA_TRIGGERSOURCE_24, DMA_SIZE_SRCWORD_DSTWORD, DMA_TRIGGER_RISINGEDGE); /* * Base Address for the DMA Module * Configure DMA channel 0 * Use ADC10 Memory Buffer as source * Increment destination address after every transfer */ DMA_setSrcAddress(__MSP430_BASEADDRESS_DMAX_3__, DMA_CHANNEL_0, ADC10_getMemoryAddressForDMA(__MSP430_BASEADDRESS_ADC10_A__), DMA_DIRECTION_UNCHANGED); /* * Base Address for the DMA Module * Configure DMA channel 0 * Use ADC_Result[0] as destination * Increment destination address after every transfer */ DMA_setDstAddress(__MSP430_BASEADDRESS_DMAX_3__, DMA_CHANNEL_0, (unsigned long)&ADC_Result[0], DMA_DIRECTION_INCREMENT); //Enable DMA channel 0 interrupt DMA_enableInterrupt(__MSP430_BASEADDRESS_DMAX_3__, DMA_CHANNEL_0); //Enable transfers on DMA channel 0 DMA_enableTransfers(__MSP430_BASEADDRESS_DMAX_3__, DMA_CHANNEL_0); while (1) { //Enable and Start the conversion //in Repeated Single-Channel Conversion Mode ADC10_startConversion(__MSP430_BASEADDRESS_ADC10_A__, ADC10_REPEATED_SINGLECHANNEL); __bis_SR_register(CPUOFF + GIE); //LPM0, ADC10_ISR will force exit __no_operation(); //For debug only //Clear accumulate register ADC_Result_sum = 0x0; for (i = 0; i < 64; i++){ ADC_Result_sum += ADC_Result[i]; } //Average of 64 conversions results ADC_Result_Average = ADC_Result_sum >> 6; //SET BREAKPOINT HERE to be able to watch ADC_Result_Average //Delay before next 64 conversions __delay_cycles(50000); } }