/* ADC SYNC sample command only This function is exported for DCL only */ kal_uint16 ADC_SYNC_Data(kal_uint16 channel){ kal_uint16 data; #if defined(DRV_ADC_NOT_EXIST) return 0; #endif // #if defined(DRV_ADC_NOT_EXIST) #ifndef DRV_ADC_NOT_EXIST adc_channel_number_check(channel); // Add PMIC ADC measurement circuit turn on here adcsche_adc_measure_en(KAL_TRUE); #if defined(DRV_ADC_FULL_FUNC) DRV_ADC_SetBits(AUXADC_SYNC, (1<<channel)); //DRV_ADC_Reg(AUXADC_SYNC) |= (1<<channel); while(DRV_ADC_Reg(AUXADC_SYNC)&(1<<channel)); data = DRV_ADC_Reg(AUXADC_DAT(channel)); #endif // #if defined(DRV_ADC_FULL_FUNC) // Add PMIC ADC measurement circuit turn off here #if !defined(DRV_ADC_MODEM_SIDE) //don't write pmu bit to 0 adcsche_adc_measure_en(KAL_FALSE); #endif return data; #endif // #ifndef DRV_ADC_NOT_EXIST }
/*must add power on function before this function*/ kal_uint16 ADC_Sync_GetData(kal_uint32 sel) { kal_uint16 data; kal_uint32 i; DRV_ADC_SetBits(AUXADC_SYNC, (1<<sel)); //kal_sleep_task(1); for(i=100;i!=0;i--); while(DRV_ADC_Reg(AUXADC_SYNC)&(1<<sel)); data = DRV_ADC_Reg(AUXADC_DAT(sel)); return data; }
void ADC_IMM_Data_on_Booting(kal_uint32 channel, kal_uint32 counts, kal_uint16 *data){ kal_uint32 i,j; #if defined(DRV_ADC_NOT_EXIST) return; #endif // #if defined(DRV_ADC_NOT_EXIST) // Enalbe ADC power adc_pwrdown_disable(); #ifndef DRV_ADC_NOT_EXIST //ASSERT(channel < ADC_MAX_CHANNEL); adc_channel_number_check(channel); // Add PMIC ADC measurement circuit turn on here adcsche_adc_measure_en(KAL_TRUE); for(j=0;j<counts;j++) { #if defined(DRV_ADC_NO_IMM) || defined(FPGA) DRV_ADC_WriteReg(AUXADC_CTRL,channel); while(!(DRV_ADC_Reg(AUXADC_STAT) & AUXADC_STAT_RDY)); data += DRV_ADC_Reg(AUXADC_DATA); #endif // #if defined(DRV_ADC_NO_IMM) || defined(FPGA) #if defined(DRV_ADC_IMM) DRV_ADC_WriteReg(AUXADC_IMM, 0); adc_dummy_read(); DRV_ADC_SetBits(AUXADC_IMM, (1<<channel)); adc_dummy_read(); // make sure the write command is finish for(i=100; i!=0; i--); while((DRV_ADC_Reg(AUXADC_CON) & AUXADC_CON_RUN)); *(data+j) = DRV_ADC_Reg(AUXADC_DAT(channel)); #endif // #if defined(DRV_ADC_IMM) } // Add PMIC ADC measurement circuit turn off here #if !defined(DRV_ADC_MODEM_SIDE) //don't write pmu bit to 0 adcsche_adc_measure_en(KAL_FALSE); #endif adc_pwrdown_enable(); #endif // #ifndef DRV_ADC_NOT_EXIST }
void ADC_IMM_Data_on_Booting(kal_uint32 channel, kal_uint32 counts, kal_uint16 *data){ #ifndef DRV_ADC_NOT_EXIST volatile kal_uint32 i; kal_uint32 j; #endif //#ifndef DRV_ADC_NOT_EXIST #if defined(DRV_ADC_NOT_EXIST) return; #endif // #if defined(DRV_ADC_NOT_EXIST) // Enalbe ADC power adc_pwrdown_disable(); #ifndef DRV_ADC_NOT_EXIST ASSERT(channel < ADC_MAX_CHANNEL); // Add PMIC ADC measurement circuit turn on here adcsche_adc_measure_en(KAL_TRUE); for(j=0;j<counts;j++) { #if defined(DRV_ADC_NO_IMM) || defined(FPGA) DRV_ADC_WriteReg(AUXADC_CTRL,channel); while(!(DRV_ADC_Reg(AUXADC_STAT) & AUXADC_STAT_RDY)); data += DRV_ADC_Reg(AUXADC_DATA); #endif // #if defined(DRV_ADC_NO_IMM) || defined(FPGA) #if defined(DRV_ADC_IMM) DRV_ADC_WriteReg(AUXADC_IMM, 0); DRV_ADC_SetBits(AUXADC_IMM, (1<<channel)); for(i=100;i!=0;i--); /* delay for avoid reading invalid status bit */ while((DRV_ADC_Reg(AUXADC_CON) & AUXADC_CON_RUN)); *(data+j) = DRV_ADC_Reg(AUXADC_DAT(channel)); #endif // #if defined(DRV_ADC_IMM) } // Add PMIC ADC measurement circuit turn off here #if !defined(DRV_ADC_MODEM_SIDE) //don't write pmu bit to 0 adcsche_adc_measure_en(KAL_FALSE); #endif #endif // #ifndef DRV_ADC_NOT_EXIST }
/* ADC IMM sample command only This function is exported for DCL only */ kal_uint16 ADC_IMM_Data(kal_uint16 channel){ #ifndef DRV_ADC_NOT_EXIST kal_uint16 data; kal_uint32 i; #endif //#ifndef DRV_ADC_NOT_EXIST #if defined(DRV_ADC_NOT_EXIST) return 0; #endif // #if defined(DRV_ADC_NOT_EXIST) #ifndef DRV_ADC_NOT_EXIST ASSERT(channel < ADC_MAX_CHANNEL); // Add PMIC ADC measurement circuit turn on here adcsche_adc_measure_en(KAL_TRUE); #if defined(DRV_ADC_NO_IMM) || defined(FPGA) DRV_ADC_WriteReg(AUXADC_CTRL,channel); while(!(DRV_ADC_Reg(AUXADC_STAT) & AUXADC_STAT_RDY)); data = DRV_ADC_Reg(AUXADC_DATA); #endif // #if defined(DRV_ADC_NO_IMM) || defined(FPGA) #if defined(DRV_ADC_IMM) DRV_ADC_WriteReg(AUXADC_IMM, 0); //DRV_ADC_Reg(AUXADC_IMM) = 0; DRV_ADC_SetBits(AUXADC_IMM, (1<<channel)); //DRV_ADC_Reg(AUXADC_IMM) |= (1<<channel); for(i=100;i!=0;i--); /* delay for avoid reading invalid status bit */ while((DRV_ADC_Reg(AUXADC_CON) & AUXADC_CON_RUN)); data = DRV_ADC_Reg(AUXADC_DAT(channel)); #endif // #if defined(DRV_ADC_IMM) // Add PMIC ADC measurement circuit turn off here #if !defined(DRV_ADC_MODEM_SIDE) //don't write pmu bit to 0 adcsche_adc_measure_en(KAL_FALSE); #endif return data; #endif // #ifndef DRV_ADC_NOT_EXIST }
kal_uint16 ADC_GetData(kal_uint8 sel) { #if defined(DRV_ADC_NOT_EXIST) return 0; #endif // #if defined(DRV_ADC_NOT_EXIST) #ifndef DRV_ADC_NOT_EXIST #if defined(DRV_ADC_MODEM_SIDE) kal_uint32 saved_current_time = 0; #endif kal_uint16 data; #if !defined(ADC_REMOVE_IRQMASK) kal_uint32 savedMask; #endif //#if !defined(ADC_REMOVE_IRQMASK) #if defined(DRV_MT6268A_ADC_TP_MIXED_ISSUE_WA) kal_uint32 savedMask2; #endif // #if defined(DRV_MT6268A_ADC_TP_MIXED_ISSUE_WA) adc_channel_number_check(sel); #if defined(DRV_ADC_NO_IMM) || defined(FPGA) ADCSAVEANDSETIRQMASK(savedMask); //savedMask = SaveAndSetIRQMask(); adc_pwrdown_disable(); #ifndef DRV_ADC_MODEM_SIDE DRV_ADC_WriteReg(AUXADC_CTRL,sel); #endif // #ifndef DRV_ADC_MODEM_SIDE adc_imm_mode_cnt++; ADCRESTOREIRQMASK(savedMask); //RestoreIRQMask(savedMask); while(!(DRV_ADC_Reg(AUXADC_STAT) & AUXADC_STAT_RDY)); data = DRV_ADC_Reg(AUXADC_DATA); #endif /*(DRV_ADC_NO_IMM,FPGA)*/ #if defined(DRV_ADC_IMM) ADCSAVEANDSETIRQMASK(savedMask); //savedMask = SaveAndSetIRQMask(); adc_imm_mode_cnt++; adcsche_adc_measure_en(KAL_TRUE); ADCRESTOREIRQMASK(savedMask); //RestoreIRQMask(savedMask); #if defined(__DRV_ADC_PMIC_TURN_ON_MEASURE_DELAY__) if((ADC_VBAT == sel) || (ADC_VISENSE == sel) || (ADC_VCHARGER == sel)) { kal_sleep_task(1); //delay 2 frames for HEPHAESTUS68 need delay to measure } #endif //#if defined(__DRV_ADC_PMIC_TURN_ON_MEASURE_DELAY__) ADCSAVEANDSETIRQMASK(savedMask); //savedMask = SaveAndSetIRQMask(); adc_pwrdown_disable(); #if defined(DRV_MT6268A_ADC_TP_MIXED_ISSUE_WA) { savedMask2 = SaveAndSetIRQMask(); } #endif // #if defined(DRV_MT6268A_ADC_TP_MIXED_ISSUE_WA) #if defined(DRV_ADC_VCHARGER_EXTEND_READING) if(ADC_VCHARGER == sel) { DRV_ADC_SetBits(MIX_ABB_base + 0x0b00,0x01f0); //extend to MAX ticks while reading } #endif #ifdef DRV_ADC_SET_CLR DRV_ADC_SetBits(AUXADC_CON1_CLR, (1<<sel)); DRV_ADC_SetBits(AUXADC_CON1_SET, (1<<sel)); #else DRV_ADC_WriteReg(AUXADC_IMM, 0); adc_dummy_read(); //DRV_ADC_Reg(AUXADC_IMM) = 0; DRV_ADC_SetBits(AUXADC_IMM, (1<<sel)); //DRV_ADC_Reg(AUXADC_IMM) |= (1<<sel); #endif ADCRESTOREIRQMASK(savedMask); //RestoreIRQMask(savedMask); #if defined(DRV_MT6268A_ADC_TP_MIXED_ISSUE_WA) { volatile kal_uint32 tmp_32; for (tmp_32=20;tmp_32!=0;tmp_32--){ ; } } #endif // #if defined(DRV_MT6268A_ADC_TP_MIXED_ISSUE_WA) #if defined(DRV_MT6268A_ADC_TP_MIXED_ISSUE_WA) { RestoreIRQMask(savedMask2); } #endif // #if defined(DRV_MT6268A_ADC_TP_MIXED_ISSUE_WA) #if !defined(DRV_MISC_IGNORE_ADC_RUN_STATUS_CHECK) #if defined(DRV_ADC_MODEM_SIDE) { kal_uint32 i; for(i=100;i!=0;i--); while((DRV_ADC_Reg(AUXADC_DAT(sel)) & 0x1000) == 0x1000); } #else adc_check_busy_bit(); #endif #endif // #if !defined(DRV_MISC_IGNORE_ADC_RUN_STATUS_CHECK) data = (DRV_ADC_Reg(AUXADC_DAT(sel)) & 0x0FFF); #if defined(DRV_ADC_MODEM_SIDE) saved_current_time = drv_get_current_time(); while(drv_get_duration_tick(saved_current_time, drv_get_current_time()) <= 2) // 64us { ;// Polling 32K reference clock } #endif #endif /*DRV_ADC_IMM*/ ADCSAVEANDSETIRQMASK(savedMask); //savedMask = SaveAndSetIRQMask(); adc_imm_mode_cnt--; if ((((kal_uint16)adc_imm_mode_cnt) == 0) && (((kal_bool)adc_sync_mode_on) == KAL_FALSE)) { adc_pwrdown_enable(); } ADCRESTOREIRQMASK(savedMask); //RestoreIRQMask(savedMask); ADCSAVEANDSETIRQMASK(savedMask); //savedMask = SaveAndSetIRQMask(); if ((((kal_uint16)adc_imm_mode_cnt) == 0) && (((kal_bool)adc_sync_mode_on) == KAL_FALSE)) { #if !defined(DRV_ADC_MODEM_SIDE) //don't write pmu bit to 0 adcsche_adc_measure_en(KAL_FALSE); #endif } ADCRESTOREIRQMASK(savedMask); //RestoreIRQMask(savedMask); return data; #endif // #ifndef DRV_ADC_NOT_EXIST }
/* * FUNCTION * adc_pwrdown_disable * * DESCRIPTION * This function is to disable adc power down control * * CALLS * * PARAMETERS * None * * RETURNS * None * * GLOBALS AFFECTED * Note that this function must be called between SaveAndSetIRQMask() * and RestoreIRQMask(). */ void adc_pwrdown_disable(void) { #ifndef DRV_ADC_NOT_EXIST #if defined(__OLD_PDN_ARCH__) #ifdef ADC_DRVPDN_FAST DRVPDN_DISABLE2(ADC_CG_PDN_CON_ADDR,ADC_CG_PDN_CON_BIT,PDN_ADC); #else /*ADC_DRVPDN_FAST*/ DRVPDN_Disable(ADC_CG_PDN_CON_ADDR,ADC_CG_PDN_CON_BIT,PDN_ADC); #endif /*ADC_DRVPDN_FAST*/ #else // #if defined(__OLD_PDN_ARCH__) #ifdef ADC_DRVPDN_FAST DRVPDN_DISABLE2(PDN_ADC); #else /*ADC_DRVPDN_FAST*/ #if !defined(__DRV_SUPPORT_LPWR__) PDN_CLR(PDN_ADC); L1SM_SleepDisable(ADCSM_handler); #else DRVPDN_Disable(PDN_ADC); #endif //#if !defined(__DRV_SUPPORT_LPWR__) #endif /*ADC_DRVPDN_FAST*/ #endif // #if defined(__OLD_PDN_ARCH__) #if defined(DRV_DIE_TO_DIE_INTERFACE) { kal_uint32 mask; mask = SaveAndSetIRQMask(); auxadc_die2die_enable = KAL_TRUE; PDN_CLR(PDN_ADC); // TP use the AuxADC PDN, make sure the PDN is disable DRV_ADC_SetBits(ABB_WR_PATH0, F26M_CLK_EN); //enable clock for die to die interface, MT6250E1 //DRV_ADC_SetBits(ABB_RSV_CON1, AUXADC_FSM_CTRL|AUXADC_26M_CLK_CTRL); //enable clock for die to die interface, MT6250E2 DRV_ADC_SetBits(ABB_RSV_CON1, AUXADC_26M_CLK_CTRL); //enable clock for die to die interface, MT6250E2 ust_busy_wait(2); DRV_ADC_SetBits(ABB_RSV_CON1, AUXADC_FSM_CTRL); //enable clock for die to die interface, MT6250E2 DRV_ADC_SetBits(0xa0160020,0x8000); DRV_ADC_SetBits(ABBA_WR_PATH0, ABBA_AUX_PWDB); // enable clock for auxadc analog interface logic DRV_ADC_SetBits(ABB_WR_PATH0, AUX_PWDB); //triggle die to die interface to send and receive auxadc data ust_busy_wait(8); DRV_ADC_SetBits(ABB_AUX_CON0, AUX_FIFO_CLK_EN); // auxadc fifo enable DRV_ADC_SetBits(ABB_AUX_CON0, AUX_FIFO_EN); // auxadc fifo enable RestoreIRQMask(mask); } #elif defined(DRV_DIE_TO_DIE_INTERFACE_V2) { DRV_ADC_SetBits(D2D_D_APC_AUX_CON1, D2D_D_F26M_AUX_EN); DRV_ADC_SetBits(D2D_A_APC_AUD_CON1, D2D_A_AUX_EN); DRV_ADC_Reg(D2D_A_APC_AUD_CON1); DRV_ADC_SetBits(D2D_D_APC_AUX_CON1, D2D_D_AUX_EN|D2D_D_F26M_AUX_EN); } #endif #endif // #ifndef DRV_ADC_NOT_EXIST }
/* ADC IMM sample command only This function is exported for DCL only */ static void ADC_Imm_register_set(kal_uint16 channel) { DRV_ADC_WriteReg(AUXADC_IMM, 0); DRV_ADC_SetBits(AUXADC_IMM, (1<<channel)); adc_check_busy_bit(); }
void ADC_Init(void) { #if (!defined(DRV_ADC_NOT_EXIST)) && (!defined(DRV_ADC_MODEM_SIDE)) ADCSM_handler = L1SM_GetHandle(); #if defined(DRV_ADC_TDMA_TIME) adc_tdma_time_setup(0,6000); #ifndef DRV_ADC_NO_TEST_DACMON DRV_ADC_WriteReg(AUXADC_CON,(AUXADC_CON_AUTOCLR0|AUXADC_CON_AUTOCLR1|AUXADC_CON_PUWAIT_EN|AUXADC_CON_TESTDACMON|0x0018)); #endif // #ifndef DRV_ADC_NO_TEST_DACMON #if defined(DRV_ADC_SW_RESET) DRV_ADC_WriteReg(AUXADC_CON,(AUXADC_CON_AUTOCLR0|AUXADC_CON_AUTOCLR1|AUXADC_CON_PUWAIT_EN)); #endif // #if defined(DRV_ADC_SW_RESET) #ifdef DRV_ADC_NO_PUWAIT_EN DRV_ADC_ClearBits(AUXADC_CON,AUXADC_CON_PUWAIT_EN); #endif #if defined(DRV_ADC_DELAY_FOR_ADCCAP ) /* AuxADC sampling period control */ DRV_ADC_SetBits(AUX_CON2,0x0064); //delay 25us #endif #if defined(DRV_ADC_BIAS_CURRENT_ENLARGE) { ECO_VERSION MT6276ipVersion = INT_ecoVersion(); if(ECO_E2 == MT6276ipVersion) { DRV_ADC_WriteReg((MIX_ABB_base + 0x0B00),0x0022); //AUX_CON0 } } #endif #ifndef DRV_ADC_NO_ADC_DEF_CONFIG #if defined(DRV_AUX_AC_CON_DEF_F) /*AUX_AC_CON*/ DRV_ADC_WriteReg(0x80500700,0x00f); #endif #if defined(DRV_AUX_AC_CON_DEF_0) /*AUX_AC_CON*/ DRV_ADC_WriteReg(0x80500700,0x0); #endif #if defined(DRV_AUX_AC_CON_DEF_X) /*AUX_AC_CON*/ if(DRV_ADC_Reg(0x80500004)==0x8c01) { DRV_ADC_WriteReg(0x80500700,0xf); } else if(DRV_ADC_Reg(0x80500004)==0x8d00) { DRV_ADC_WriteReg(0x80500700,0x0); } else if(DRV_ADC_Reg(0x80500004)==0x8d01) { DRV_ADC_WriteReg(0x80500700,0x0); } #endif /*DRV_AUX_AC_CON_DEF_X*/ #endif // #ifndef DRV_ADC_NO_ADC_DEF_CONFIG #endif /*DRV_ADC_TDMA_TIME*/ #endif // #if (!defined(DRV_ADC_NOT_EXIST)) && (!defined(DRV_ADC_MODEM_SIDE)) }