void GIF_GetInfo(gif_info_struct *out)
{
kal_uint32 reg;
// Image descriptor
reg = DRV_Reg32(GIF_IMG_REG_1);
out->height = (kal_uint16)(reg & 0xFFFF);
out->width = (kal_uint16)(reg >> 16);
reg = DRV_Reg32(GIF_IMG_REG_2);
out->y = (kal_uint16)(reg & 0xFFFF);
out->x = (kal_uint16)(reg >> 16);
reg = DRV_Reg32(GIF_IMG_REG_3);
out->LCT_size = (reg & GIF_IMG_REG3_LCT_SIZE);
out->interlace = (reg & GIF_IMG_REG3_LCT_INTERLACE) >> 6;
out->LCT_flag = (reg & GIF_IMG_REG3_LCT_FLG) >> 7;
// Logical screen descriptor
reg = DRV_Reg32(GIF_LSD_REG_1);
out->lheight = (kal_uint16)(reg & 0xFFFF);
out->lwidth = (kal_uint16)(reg >> 16);
reg = DRV_Reg32(GIF_LSD_REG_2);
out->bg = (reg & GIF_LSD2_BG) >> 8;
out->GCT_size = (reg & GIF_LSD2_GCT_SIZE) >> 16;
out->bpp = (reg & GIF_LSD2_BPP) >> 20;
out->GCT_flag= (reg & GIF_LSD2_GCT_FLG) >> 23;
}
void mtk_wdt_init(void)
{
unsigned int tmp;
unsigned int interval_val = DRV_Reg32(MTK_WDT_INTERVAL);
mtk_wdt_mode_config(FALSE, FALSE, FALSE, FALSE, FALSE);
printf("UB wdt init\n");
/* Update interval register value and check reboot flag */
if( (interval_val & RGU_TRIGGER_RESET_MASK) == IS_POWER_ON_RESET )
is_rgu_trigger_rst = 0; // Power off and power on reset
else
is_rgu_trigger_rst = 1; // RGU trigger reset
interval_val &= ~(RGU_TRIGGER_RESET_MASK|MAGIC_NUM_MASK);
interval_val |= (U_BOOT_MAGIC|IS_POWER_ON_RESET);
/* Write back INTERVAL REG */
DRV_WriteReg32(MTK_WDT_INTERVAL, interval_val);
/* Setting timeout 10s */
mtk_wdt_set_time_out_value(10);
/*set spm_sysrst & pcm_wdt_rst to be reset mode*/
tmp = DRV_Reg32(MTK_WDT_REQ_IRQ_EN);
tmp |= MTK_WDT_REQ_IRQ_EN_KEY;
tmp &= ~(MTK_WDT_REQ_IRQ_EN_SPM | MTK_WDT_REQ_IRQ_EN_PCM);
DRV_WriteReg32(MTK_WDT_REQ_IRQ_EN, tmp);
mtk_wdt_mode_config(TRUE, TRUE, FALSE, FALSE, TRUE);
mtk_wdt_restart();
}
static void __gpt_get_cnt(struct gpt_device *dev, unsigned int *ptr)
{
*ptr = DRV_Reg32(dev->base_addr + GPT_CNT);
if (dev->features & GPT_FEAT_64_BIT) {
*(++ptr) = DRV_Reg32(dev->base_addr + GPT_CNTH);
}
}
static void mt_fh_hal_popod_save(void)
{
const unsigned int pll_id = FH_MAIN_PLLID;
FH_MSG_DEBUG("EN: %s",__func__);
//disable maipll SSC mode
if(g_fh_pll[pll_id].fh_status == FH_FH_ENABLE_SSC){
unsigned int fh_dds = 0;
unsigned int pll_dds = 0;
const unsigned int reg_cfg = g_reg_cfg[pll_id];
//only when SSC is enable, turn off MAINPLL hopping
fh_set_field(reg_cfg, FH_FRDDSX_EN, 0); //disable SSC mode
fh_set_field(reg_cfg, FH_SFSTRX_EN, 0); //disable dvfs mode
fh_set_field(reg_cfg, FH_FHCTLX_EN, 0); //disable hopping control
pll_dds = (DRV_Reg32(g_reg_dds[pll_id])) & MASK21b;
fh_dds = (DRV_Reg32(g_reg_mon[pll_id])) & MASK21b;
FH_MSG("Org pll_dds:%x fh_dds:%x",pll_dds,fh_dds);
wait_dds_stable(pll_dds, g_reg_mon[pll_id], 100);
//write back to ncpo
fh_write32(g_reg_pll_con1[pll_id],
(fh_read32(g_reg_dds[pll_id])&MASK21b)|(fh_read32(MAINPLL_CON1)&0xFFE00000)|(BIT32));
FH_MSG("MAINPLL_CON1: 0x%08x",(fh_read32(g_reg_pll_con1[pll_id])&MASK21b));
// switch to register control
fh_switch2fhctl(pll_id,0);
mb();
}
}
static ssize_t cpu_ss_mode_write(struct file *file, const char *buffer, unsigned long count, void *data)
{
int len = 0, mode = 0;
char desc[32];
len = (count < (sizeof(desc) - 1)) ? count : (sizeof(desc) - 1);
if (copy_from_user(desc, buffer, len))
{
return 0;
}
desc[len] = '\0';
if (sscanf(desc, "%d", &mode) == 1)
{
if (mode)
{
printk("[%s]: config cpu speed switch mode = ARMPLL\n", __FUNCTION__);
mt65xx_reg_sync_writel((DRV_Reg32(TOP_CKMUXSEL) | 0x0004), TOP_CKMUXSEL);
}
else
{
printk("[%s]: config cpu speed switch mode = CLKSQ\n", __FUNCTION__);
mt65xx_reg_sync_writel((DRV_Reg32(TOP_CKMUXSEL) & 0x0ff3), TOP_CKMUXSEL);
}
return count;
}
else
{
printk("[%s]: bad argument!! should be \"1\" or \"0\"\n", __FUNCTION__);
}
return -EINVAL;
}
int mt_cpu_ss_thread_handler(void *unused)
{
kal_uint32 flag = 0;
do
{
ktime_t ktime = ktime_set(mt_cpu_ss_period_s, mt_cpu_ss_period_ns);
wait_event_interruptible(mt_cpu_ss_timer_waiter, mt_cpu_ss_timer_flag != 0);
mt_cpu_ss_timer_flag = 0;
if (!flag)
{
mt65xx_reg_sync_writel((DRV_Reg32(TOP_CKMUXSEL) & 0x0ff3), TOP_CKMUXSEL);
flag = 1;
}
else
{
mt65xx_reg_sync_writel((DRV_Reg32(TOP_CKMUXSEL) | 0x0004), TOP_CKMUXSEL);
flag = 0;
}
if (mt_cpu_ss_debug_mode)
printk("[%s]: TOP_CKMUXSEL = 0x%x\n", __FUNCTION__, DRV_Reg32(TOP_CKMUXSEL));
hrtimer_start(&mt_cpu_ss_timer, ktime, HRTIMER_MODE_REL);
} while (!kthread_should_stop());
return 0;
}
void mt_mempll_ssc(void)
{
#if !defined(__FPGA__)
kal_uint32 reg_val;
// MT6290(M), Not E1, Because MT6290(M)E1 has WMHEC5471
if ((DRV_Reg32(HW_CODE_VERSION) == 0x00006290) && (DRV_Reg32(HW_VERSION) != 0x0000CA00)) {
reg_val = DRV_Reg32(REG_MDCLKCTL_EMIDDS_FH_CTL2) & ~(EMIDDS_FH_CTL2_FRDDS_DNLMT_MASK | EMIDDS_FH_CTL2_FRDDS_UPLMT_MASK);
if (TRUE == is_mt6290m) {
// -8%. For PCW is equal to 25MHz, down limit is 2 MHz, Up limit is 0 MHz
//reg_val |= EMIDDS_FH_CTL2_FRDDS_DNLMT(0x9E) | EMIDDS_FH_CTL2_FRDDS_UPLMT(0x0);
// -4%. For PCW is equal to 25MHz, down limit is 2 MHz, Up limit is 0 MHz
reg_val |= EMIDDS_FH_CTL2_FRDDS_DNLMT(0x4F) | EMIDDS_FH_CTL2_FRDDS_UPLMT(0x0);
} else {
// -8%. For PCW is equal to 27.79167MHz, down limit is 2.2 MHz, Up limit is 0 MHz
//reg_val |= EMIDDS_FH_CTL2_FRDDS_DNLMT(0xB0) | EMIDDS_FH_CTL2_FRDDS_UPLMT(0x0);
// -4%. For PCW is equal to 27.79167MHz, down limit is 1.1 MHz, Up limit is 0 MHz
reg_val |= EMIDDS_FH_CTL2_FRDDS_DNLMT(0x58) | EMIDDS_FH_CTL2_FRDDS_UPLMT(0x0);
}
DRV_WriteReg32(REG_MDCLKCTL_EMIDDS_FH_CTL2, reg_val);
// Time Step is 0.5 us, Frequency Step is ~0.1MHz
reg_val = DRV_Reg32(REG_MDCLKCTL_EMIDDS_FH_CTL1) & ~(EMIDDS_FH_CTL1_EMIDDS_FRDDS_DTS_MASK | EMIDDS_FH_CTL1_EMIDDS_FRDDS_DYS_MASK);
reg_val |= EMIDDS_FH_CTL1_EMIDDS_FSM_EN | EMIDDS_FH_CTL1_EMIDDS_FRDDS_EN | \
EMIDDS_FH_CTL1_EMIDDS_FRDDS_DTS(0) | EMIDDS_FH_CTL1_EMIDDS_FRDDS_DYS(0);
DRV_WriteReg32(REG_MDCLKCTL_EMIDDS_FH_CTL1, reg_val);
// We need to write EMIDDS_CTL to mask sure that previous settings take effect
reg_val = DRV_Reg32(REG_MDCLKCTL_EMIDDS_CTL) | EMIDDS_SDM_PCW_CHG;
DRV_WriteReg32_NPW(REG_MDCLKCTL_EMIDDS_CTL, reg_val);
Data_Mem_Barrier();
}
#endif // end if !defined(__FPGA__)
}
static int mt_fh_hal_dfs_mpll(unsigned int target_dds)
{
unsigned long flags = 0;
const unsigned int pll_id = FH_M_PLLID;
const unsigned int reg_cfg = g_reg_cfg[pll_id];
FH_MSG("%s, current dds(MPLL_CON1): 0x%x, target dds %d",
__func__,(fh_read32(g_reg_pll_con1[pll_id])&MASK21b),
target_dds);
spin_lock_irqsave(&g_fh_lock, flags);
if(g_fh_pll[pll_id].fh_status == FH_FH_ENABLE_SSC){
unsigned int pll_dds = 0;
unsigned int fh_dds = 0;
fh_set_field(reg_cfg, FH_FRDDSX_EN, 0); //disable SSC mode
fh_set_field(reg_cfg, FH_SFSTRX_EN, 0); //disable dvfs mode
fh_set_field(reg_cfg, FH_FHCTLX_EN, 0); //disable hopping control
pll_dds = (DRV_Reg32(g_reg_dds[pll_id])) & MASK21b;
fh_dds = (DRV_Reg32(g_reg_mon[pll_id])) & MASK21b;
FH_MSG(">p:f< %x:%x",pll_dds,fh_dds);
wait_dds_stable(pll_dds, g_reg_mon[pll_id], 100);
}
mt_fh_hal_dvfs(pll_id, target_dds);
if(g_fh_pll[pll_id].fh_status == FH_FH_ENABLE_SSC){
const struct freqhopping_ssc* p_setting = &ssc_mpll_setting[2];
fh_set_field(reg_cfg, FH_FRDDSX_EN, 0); //disable SSC mode
fh_set_field(reg_cfg, FH_SFSTRX_EN, 0); //disable dvfs mode
fh_set_field(reg_cfg, FH_FHCTLX_EN, 0); //disable hopping control
fh_sync_ncpo_to_fhctl_dds(pll_id);
FH_MSG("Enable mpll SSC mode");
FH_MSG("DDS: 0x%08x", (fh_read32(g_reg_dds[pll_id])&MASK21b));
fh_set_field(reg_cfg,MASK_FRDDSX_DYS,p_setting->df);
fh_set_field(reg_cfg,MASK_FRDDSX_DTS,p_setting->dt);
fh_write32(g_reg_updnlmt[pll_id],
(PERCENT_TO_DDSLMT((fh_read32(g_reg_dds[pll_id])&MASK21b), p_setting->lowbnd) << 16));
FH_MSG("UPDNLMT: 0x%08x", fh_read32(g_reg_updnlmt[pll_id]));
fh_switch2fhctl(pll_id, 1);
fh_set_field(reg_cfg, FH_FRDDSX_EN, 1); //enable SSC mode
fh_set_field(reg_cfg, FH_FHCTLX_EN, 1); //enable hopping control
FH_MSG("CFG: 0x%08x", fh_read32(reg_cfg));
}
spin_unlock_irqrestore(&g_fh_lock, flags);
return 0;
}
static void spm_wdt_init(void)
{
unsigned int tmp;
// set scpsys reset mode , not trigger irq
tmp = DRV_Reg32(MTK_WDT_REQ_MODE);
tmp |= MTK_WDT_REQ_MODE_KEY;
tmp |= (MTK_WDT_REQ_MODE_SPM_SCPSYS);
DRV_WriteReg32(MTK_WDT_REQ_MODE,tmp);
tmp = DRV_Reg32(MTK_WDT_REQ_IRQ_EN);
tmp |= MTK_WDT_REQ_IRQ_KEY;
tmp &= ~(MTK_WDT_REQ_IRQ_SPM_SCPSYS_EN);
DRV_WriteReg32(MTK_WDT_REQ_IRQ_EN,tmp);
printk( "mtk_wdt_init [MTK_WDT] not use RGU WDT use_SPM_WDT!! ********\n" );
tmp = DRV_Reg32(MTK_WDT_MODE);
tmp |= MTK_WDT_MODE_KEY;
//disable wdt
tmp &= (~(MTK_WDT_MODE_IRQ|MTK_WDT_MODE_ENABLE|MTK_WDT_MODE_DUAL_MODE));
// Bit 4: WDT_Auto_restart, this is a reserved bit, we use it as bypass powerkey flag.
// Because HW reboot always need reboot to kernel, we set it always.
tmp |= MTK_WDT_MODE_AUTO_RESTART;
//BIt2 ext singal
tmp |= MTK_WDT_MODE_EXTEN;
DRV_WriteReg32(MTK_WDT_MODE,tmp);
}
void drv_idc_init_uart(void)
{
#if defined(MT6290)
DRV_WriteReg32(BASE_ADDR_MDINFRAMISC + 0x114, DRV_Reg32(BASE_ADDR_MDINFRAMISC + 0x114) | 0x6);
DRV_WriteReg32(BASE_ADDR_MDPERIMISC + 0x114, DRV_Reg32(BASE_ADDR_MDPERIMISC + 0x114) | 0x4);
#if __FPGA__
#else
// set GPIO as default output
DRV_WriteReg32_NPW(BASE_ADDR_TOPMISC + 0x1D4, DRV_Reg32(BASE_ADDR_TOPMISC + 0x1D4) | 0x200);
#endif
#endif
#if defined(MT6595)
// Enable GPIO 29, 30 pull-up/pull-down
DRV_WriteReg32(GPIO_base + 0x110, DRV_Reg32(GPIO_base + 0x110) | 0x6000);
// Select GPIO 29, 30 pull-up
DRV_WriteReg32(GPIO_base + 0x210, DRV_Reg32(GPIO_base + 0x210) | 0x6000);
#endif
#if !defined(ATEST_DRV_ENABLE)
dhl_trace(TRACE_INFO, 0, IDC_UART_INIT_MSG);
#else
kal_sprintf(idc_dbg_str, "drv_idc: IDC UART Init\n\r");
DT_IDC_PRINTF(idc_dbg_str);
#endif
// register isr, enable RX data receive interrupt
IRQMask(MD_IRQID_IDC2ARM);
// Initialize IDC UART FIFO threshold
drv_idc_set_fifo_trigger(1);
DRV_WriteReg32(IDC_UART_FCR, IDC_UART_FCR_RXTRIG | IDC_UART_FCR_FIFOINI);
DRV_WriteReg32(IDC_UART_IER, IDC_UART_IER_ERBFI);
IRQ_Register_LISR(MD_IRQID_IDC2ARM, idc_uart_lisr, "IDC_UART");
DRV_Register_HISR(DRV_IDC_HISR_ID, idc_uart_hisr);
IRQSensitivity(MD_IRQID_IDC2ARM, KAL_FALSE);
IRQClearInt(MD_IRQID_IDC2ARM);
IRQUnmask(MD_IRQID_IDC2ARM);
idc_port.intr_en = KAL_TRUE;
idc_port.schedule_state[0] = IDC_PLAN;
idc_port.schedule_state[1] = IDC_PLAN;
idc_port.event_cnt[0] = 0;
idc_port.event_cnt[1] = 0;
idc_port.sram_w_ptr = 3; // 2'b11
idc_port.sram_usage_bit_map[0] = 0;
idc_port.sram_usage_bit_map[1] = 0;
idc_port.rx_buf = 0;
// Initialize baud rate
drv_idc_set_baudrate(4000000);
// initial flags/config of IDC driver
idc_port.main_state = IDC_IN_USE;
return;
}
/*
* mt6577_irq_mask_all: mask all IRQ lines. (This is ONLY used for the idle current measurement by the factory mode.)
* @mask: pointer to struct mtk_irq_mask for storing the original mask value.
* Return 0 for success; return negative values for failure.
*/
int mt6577_irq_mask_all(struct mtk_irq_mask *mask)
{
unsigned long flags;
if (mask) {
mask->mask0 = DRV_Reg32(GIC_ICDISER0);
mask->mask1 = DRV_Reg32(GIC_ICDISER1);
mask->mask2 = DRV_Reg32(GIC_ICDISER2);
mask->mask3 = DRV_Reg32(GIC_ICDISER3);
mask->mask4 = DRV_Reg32(GIC_ICDISER4);
DRV_WriteReg32(GIC_ICDICER0, 0xFFFFFFFF);
DRV_WriteReg32(GIC_ICDICER1, 0xFFFFFFFF);
DRV_WriteReg32(GIC_ICDICER2, 0xFFFFFFFF);
DRV_WriteReg32(GIC_ICDICER3, 0xFFFFFFFF);
DRV_WriteReg32(GIC_ICDICER4, 0xFFFFFFFF);
dsb();
mask->header = IRQ_MASK_HEADER;
mask->footer = IRQ_MASK_FOOTER;
return 0;
} else {
return -1;
}
}
static int primary_cpu_enter_wfi(void *data)
{
#if 0
int i = 0;
#endif
unsigned int irqstat = 0;
int cpu = *(int*)data;
dcm_info("[%s]: thread idle-%d start\n", __func__, cpu);
#ifdef CONFIG_LOCAL_WDT
mpcore_wk_wdt_stop();
#endif
mt6577_irq_mask_all(&cpu_irq_mask[cpu]);
mt6577_irq_unmask_for_sleep(MT6577_KP_IRQ_ID);
dcm_info("[%s]: cpu%d waiting all threads done\n", __func__, cpu);
complete(&each_thread_done[cpu]);
wait_for_completion(&all_threads_done);
local_irq_disable();
dcm_info("[%s]: cpu%d before wfi\n", __func__, cpu);
#if 0
do {
go_to_idle();
irqstat = DRV_Reg32(GIC_CPU_BASE + GIC_CPU_INTACK) & 0x3FF;
dcm_info("[%s]: cpu%d after wfi(irqstat:0x%x/%u)\n", __func__, cpu, irqstat, irqstat);
if (irqstat == MT6577_KP_IRQ_ID) {
break;
}
} while (1);
#else
go_to_idle();
irqstat = DRV_Reg32(GIC_CPU_BASE + GIC_CPU_INTACK) & 0x3FF;
dcm_info("[%s]: cpu%d after wfi(irqstat:0x%x/%u)\n", __func__, cpu, irqstat, irqstat);
#endif
local_irq_enable();
spin_lock(&factory_lock);
mt6577_irq_mask_restore(&cpu_irq_mask[cpu]);
spin_unlock(&factory_lock);
#if 0
for (i = 1; i < nr_cpu_ids; i++) {
wake_flag[i] = 1;
smp_send_reschedule(i);
}
#endif
#if defined(CONFIG_MTK_LEDS)
mt65xx_leds_brightness_set(MT65XX_LED_TYPE_LCD, LED_FULL);
#endif
dcm_info("[%s]: thread idle-%d end\n", __func__, cpu);
return 0;
}
void drv_idc_get_schedule_status(kal_uint32 *schedule_status)
{
schedule_status[0] = DRV_Reg32(IDC_BSI_SCH_STATUS_3100);
schedule_status[1] = DRV_Reg32(IDC_BSI_SCH_STATUS_6332) & ~0xFC000000; // 58 ~ 63 is reserved for other utility
dhl_trace(TRACE_INFO, 0, IDC_SCHEDULE_STATUS_MSG, schedule_status[0], schedule_status[1]);
return;
}
int mtk_wdt_swsysret_config(int bit,int set_value)
{
unsigned int wdt_sys_val;
spin_lock(&rgu_reg_operation_spinlock);
printk("mtk_wdt_swsysret_config(0x%x,0x%x) \n",bit,set_value);
switch(bit)
{
case MTK_WDT_SWSYS_RST_MD_RST:
wdt_sys_val = DRV_Reg32(MTK_WDT_SWSYSRST);
printk("fwq2 before set wdt_sys_val =%x\n",wdt_sys_val);
wdt_sys_val |= MTK_WDT_SWSYS_RST_KEY;
if(1==set_value)
{
wdt_sys_val |= MTK_WDT_SWSYS_RST_MD_RST;
}
if(0==set_value)
{
wdt_sys_val &= ~MTK_WDT_SWSYS_RST_MD_RST;
}
DRV_WriteReg32(MTK_WDT_SWSYSRST,wdt_sys_val);
break;
case MTK_WDT_SWSYS_RST_MD_LITE_RST:
wdt_sys_val = DRV_Reg32(MTK_WDT_SWSYSRST);
printk("fwq2 before set wdt_sys_val =%x\n",wdt_sys_val);
wdt_sys_val |= MTK_WDT_SWSYS_RST_KEY;
if(1==set_value)
{
wdt_sys_val |= MTK_WDT_SWSYS_RST_MD_LITE_RST;
}
if(0==set_value)
{
wdt_sys_val &= ~MTK_WDT_SWSYS_RST_MD_LITE_RST;
}
DRV_WriteReg32(MTK_WDT_SWSYSRST,wdt_sys_val);
break;
case 0x30000000:
// io ring read non reset register
wdt_sys_val = DRV_Reg32(MTK_WDT_NONRST_REG);
printk("io ring read raw wdt_sys_val=0x%x",wdt_sys_val);
//wdt_sys_val = wdt_sys_val & 0xFFFF;
//printk("io ring read wdt_sys_val=0x%x",wdt_sys_val);
spin_unlock(&rgu_reg_operation_spinlock);
return wdt_sys_val;
break;
default:
printk("do not handle this command \n");
}
spin_unlock(&rgu_reg_operation_spinlock);
mdelay(10);
printk("mtk_wdt_swsysret_config done\n");
return 0;
}
unsigned int hacc_do_aes(AES_OPS ops, unsigned char *src, unsigned char *dst, unsigned int size)
{
unsigned int i;
unsigned int *ds, *dt, *vt;
/* make sure size is aligned to aes block size */
if ((size % AES_BLK_SZ) != 0) {
SMSG("[%s] size = %d is not %d bytes alignment\n", MOD, size, AES_BLK_SZ);
return ERR_HACC_DATA_UNALIGNED;
}
vt = (unsigned int *)&hacc_ctx.cfg.config[0];
/* erase src, cfg, out register */
DRV_SetReg32(HACC_ACON2, HACC_AES_CLR);
/* set init config */
for (i = 0; i < AES_CFG_SZ; i += 4)
DRV_WriteReg32(HACC_ACFG0 + i, *vt++);
if (ops == AES_ENC)
DRV_SetReg32(HACC_ACON, HACC_AES_ENC);
else
DRV_ClrReg32(HACC_ACON, HACC_AES_ENC);
ds = (unsigned int *)src;
dt = (unsigned int *)dst;
do {
/* fill in the data */
for (i = 0; i < AES_BLK_SZ; i += 4)
DRV_WriteReg32(HACC_ASRC0 + i, *ds++);
/* start aes engine */
DRV_SetReg32(HACC_ACON2, HACC_AES_START);
/* wait for aes engine ready */
while ((DRV_Reg32(HACC_ACON2) & HACC_AES_RDY) == 0)
;
/* read out the data */
for (i = 0; i < AES_BLK_SZ; i += 4)
*dt++ = DRV_Reg32(HACC_AOUT0 + i);
if (size == 0)
goto _end;
size -= AES_BLK_SZ;
} while (size != 0);
_end:
return SEC_OK;
}
static void mt_auxadc_cal_prepare(void)
{
unsigned int mt_auxadc_bgr=0;
mt_auxadc_bgr = DRV_Reg32(AUXADC_BGR);
printk("[adc_cali]:mt_auxadc_cal_prepare get AUXADC_BGR 0x%04x \n",mt_auxadc_bgr);
printk("[adc_cali]:mt_auxadc_cal_prepare get AUXADC_TS_CON0 0x%04x \n",DRV_Reg32(AUXADC_TS_CON0));
if(mt_auxadc_bgr&0xF0000000)
{
AUXADC_SET_BITS(((mt_auxadc_bgr&0xF0000000)>>16),AUXADC_TS_CON0);
}
/*******************************************************************************
* Function definitions
*******************************************************************************/
void boot_init_bus()
{
#if defined(MT6290_S00)
// For E1 Chip, Add Arbitration Issue Patch When NFI + MSDC Coexist
DRV_WriteReg32(BASE_MADDR_MDCFGCTL + 0x0030, DRV_Reg32(BASE_MADDR_MDCFGCTL + 0x0030) | (0x1 << 20)); // Set MD Own Bit
DRV_WriteReg32(BASE_MADDR_APMISC + 0x0030, 0x00000000);
DRV_WriteReg32(BASE_MADDR_MDCFGCTL + 0x0030, DRV_Reg32(BASE_MADDR_MDCFGCTL + 0x0030) & ~(0x1 << 20)); // Un-Set MD Own Bit
#else
#endif
}
void mrdump_check_ok(void)
{
if ((DRV_Reg32(MRDUMP_SIG1_ADDR) == 0x5544524d) &&
(DRV_Reg32(MRDUMP_SIG2_ADDR) == 0x3030504d))
{
DRV_WriteReg32(MRDUMP_SIG1_ADDR, 0);
DRV_WriteReg32(MRDUMP_SIG2_ADDR, 0);
g_ddr_reserve_enable = 1;
g_ddr_reserve_success = 1;
print("[MRDUMP] DDR reserve mode success.\n");
}
}
static void mtk_wdt_mode_config( BOOL dual_mode_en,
BOOL irq,
BOOL ext_en,
BOOL ext_pol,
BOOL wdt_en )
{
unsigned int tmp;
printf(" mtk_wdt_mode LK config mode value=%x\n",DRV_Reg32(MTK_WDT_MODE));
tmp = DRV_Reg32(MTK_WDT_MODE);
tmp |= MTK_WDT_MODE_KEY;
// Bit 0 : Whether enable watchdog or not
if(wdt_en == TRUE)
tmp |= MTK_WDT_MODE_ENABLE;
else
tmp &= ~MTK_WDT_MODE_ENABLE;
// Bit 1 : Configure extern reset signal polarity.
if(ext_pol == TRUE)
tmp |= MTK_WDT_MODE_EXT_POL;
else
tmp &= ~MTK_WDT_MODE_EXT_POL;
// Bit 2 : Whether enable external reset signal
if(ext_en == TRUE)
tmp |= MTK_WDT_MODE_EXTEN;
else
tmp &= ~MTK_WDT_MODE_EXTEN;
// Bit 3 : Whether generating interrupt instead of reset signal
if(irq == TRUE)
tmp |= MTK_WDT_MODE_IRQ;
else
tmp &= ~MTK_WDT_MODE_IRQ;
// Bit 6 : Whether enable debug module reset
if(dual_mode_en == TRUE)
tmp |= MTK_WDT_MODE_DUAL_MODE;
else
tmp &= ~MTK_WDT_MODE_DUAL_MODE;
// Bit 4: WDT_Auto_restart, this is a reserved bit, we use it as bypass powerkey flag.
// Because HW reboot always need reboot to kernel, we set it always.
tmp |= MTK_WDT_MODE_AUTO_RESTART;
DRV_WriteReg32(MTK_WDT_MODE,tmp);
//dual_mode(1); //always dual mode
//mdelay(100);
printf(" mtk_wdt_mode_config LK mode value=%x, tmp:%x\n",DRV_Reg32(MTK_WDT_MODE), tmp);
}
chip_ver_t platform_chip_ver(void)
{
#if 0
unsigned int hw_subcode = DRV_Reg32(APHW_SUBCODE);
unsigned int sw_ver = DRV_Reg32(APSW_VER);
#endif
/* mt6589/mt6583 share the same hw_code/hw_sub_code/hw_version/sw_version currently */
chip_ver_t ver = CHIP_6583_E1;
return ver;
}
/*
* mt_irq_mask_all: mask all IRQ lines. (This is ONLY used for the sleep driver)
* @mask: pointer to struct mtk_irq_mask for storing the original mask value.
* Return 0 for success; return negative values for failure.
*/
int mt_irq_mask_all(struct mtk_irq_mask *mask)
{
if (mask) {
mask->mask0 = DRV_Reg32(GIC_ICDISER0);
mask->mask1 = DRV_Reg32(GIC_ICDISER1);
mask->mask2 = DRV_Reg32(GIC_ICDISER2);
mask->mask3 = DRV_Reg32(GIC_ICDISER3);
mask->mask4 = DRV_Reg32(GIC_ICDISER4);
mask->mask5 = DRV_Reg32(GIC_ICDISER5);
mask->mask6 = DRV_Reg32(GIC_ICDISER6);
mask->mask7 = DRV_Reg32(GIC_ICDISER7);
DRV_WriteReg32(GIC_ICDICER0, 0xFFFFFFFF);
DRV_WriteReg32(GIC_ICDICER1, 0xFFFFFFFF);
DRV_WriteReg32(GIC_ICDICER2, 0xFFFFFFFF);
DRV_WriteReg32(GIC_ICDICER3, 0xFFFFFFFF);
DRV_WriteReg32(GIC_ICDICER4, 0xFFFFFFFF);
DRV_WriteReg32(GIC_ICDICER5, 0xFFFFFFFF);
DRV_WriteReg32(GIC_ICDICER6, 0xFFFFFFFF);
DRV_WriteReg32(GIC_ICDICER7, 0xFFFFFFFF);
dsb();
mask->header = IRQ_MASK_HEADER;
mask->footer = IRQ_MASK_FOOTER;
return 0;
} else {
return -1;
}
}
int mtk_wdt_enable(enum wk_wdt_en en)
{
unsigned int tmp =0;
spin_lock(&rgu_reg_operation_spinlock);
#ifdef CONFIG_KICK_SPM_WDT
if(WK_WDT_EN ==en)
{
spm_wdt_enable_timer();
printk("wdt enable spm timer\n");
tmp = DRV_Reg32(MTK_WDT_REQ_MODE);
tmp |= MTK_WDT_REQ_MODE_KEY;
tmp |= (MTK_WDT_REQ_MODE_SPM_SCPSYS);
DRV_WriteReg32(MTK_WDT_REQ_MODE,tmp);
g_wdt_enable = 1;
}
if(WK_WDT_DIS==en)
{
spm_wdt_disable_timer();
printk("wdt disable spm timer\n ");
tmp = DRV_Reg32(MTK_WDT_REQ_MODE);
tmp |= MTK_WDT_REQ_MODE_KEY;
tmp &= ~(MTK_WDT_REQ_MODE_SPM_SCPSYS);
DRV_WriteReg32(MTK_WDT_REQ_MODE,tmp);
g_wdt_enable = 0;
}
#else
tmp = DRV_Reg32(MTK_WDT_MODE);
tmp |= MTK_WDT_MODE_KEY;
if(WK_WDT_EN == en)
{
tmp |= MTK_WDT_MODE_ENABLE;
g_wdt_enable = 1;
}
if(WK_WDT_DIS == en)
{
tmp &= ~MTK_WDT_MODE_ENABLE;
g_wdt_enable = 0;
}
printk("mtk_wdt_enable value=%x,pid=%d\n",tmp,current->pid);
DRV_WriteReg32(MTK_WDT_MODE,tmp);
#endif
spin_unlock(&rgu_reg_operation_spinlock);
return 0;
}
static int fh_dvfs_proc_read(struct seq_file* m, void* v)
{
int i = 0;
FH_MSG("EN: %s",__func__);
seq_printf(m, "DVFS:\r\n");
seq_printf(m, "CFG: 0x3 is SSC mode; 0x5 is DVFS mode \r\n");
for(i = 0;i < FH_PLL_NUM; ++i){
seq_printf(m, "FHCTL%d: CFG:0x%08x DVFS:0x%08x\r\n",
i, DRV_Reg32(g_reg_cfg[i]), DRV_Reg32(g_reg_dvfs[i]));
}
return 0;
}
void mtk_wdt_init(void)
{
unsigned int tmp;
unsigned int nonrst;
unsigned int interval_val = DRV_Reg32(MTK_WDT_INTERVAL);
mtk_wdt_mode_config(FALSE, FALSE, FALSE, FALSE, FALSE);
WDTLOG("UB wdt init\n");
/* Update interval register value and check reboot flag */
if( (interval_val & RGU_TRIGGER_RESET_MASK) == IS_POWER_ON_RESET )
is_rgu_trigger_rst = 0; // Power off and power on reset
else
is_rgu_trigger_rst = 1; // RGU trigger reset
interval_val &= ~(RGU_TRIGGER_RESET_MASK|MAGIC_NUM_MASK);
interval_val |= (U_BOOT_MAGIC|IS_POWER_ON_RESET);
/* Write back INTERVAL REG */
DRV_WriteReg32(MTK_WDT_INTERVAL, interval_val);
/* Setting timeout 10s */
mtk_wdt_set_time_out_value(10);
#if (!LK_WDT_DISABLE)
mtk_wdt_mode_config(TRUE, TRUE, TRUE, FALSE, TRUE);
mtk_wdt_restart();
#endif
/*
* E3 ECO
* reset will delay 2ms after set SW_WDT in register
*/
nonrst = DRV_Reg32(MTK_WDT_NONRST_REG);
nonrst = (nonrst | (1<<29));
DRV_WriteReg32(MTK_WDT_NONRST_REG, nonrst);
dprintf(CRITICAL,"WDT NONRST=0x%x \n\r", DRV_Reg32(MTK_WDT_NONRST_REG));
#if 0
int i=0;
//lk wdt test
while(1)
{
i++;
mdelay(1000);
WDTLOG("UB wdt test %d\n" ,i);
/* Dump RGU regisers */
WDTLOG("==== fwq Dump RGU Reg ========\n");
WDTLOG("RGU MODE: %x\n", DRV_Reg32(MTK_WDT_MODE));
WDTLOG("RGU LENGTH: %x\n", DRV_Reg32(MTK_WDT_LENGTH));
WDTLOG("RGU STA: %x\n", DRV_Reg32(MTK_WDT_STATUS));
WDTLOG("RGU INTERVAL: %x\n", DRV_Reg32(MTK_WDT_INTERVAL));
WDTLOG("RGU SWSYSRST: %x\n", DRV_Reg32(MTK_WDT_SWSYSRST));
WDTLOG("==== Dump RGU Reg End ====\n");
if(i<60)
{
WDTLOG("kick lk ext\n" );
mtk_wdt_restart();
}
}
#endif
}
void mt6577_pmic_low_power_init(void)
{
unsigned int volt = 0, volt_bias = 0;
/********************
* PMIC VPROC setting
*********************/
upmu_buck_vosel_srclken_0(BUCK_VPROC, 0x08); // VPROC 0.9V in sleep mode
if (get_chip_ver() >= CHIP_6577_E1)
{
upmu_buck_vosel_dvs_00(BUCK_VPROC, 0x08); // 0.900V DVS_VOL_00
upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x0F); // 1.075V DVS_VOL_01
upmu_buck_vosel_dvs_10(BUCK_VPROC, 0x13); // 1.175V DVS_VOL_10
if ((DRV_Reg32(HW_RESV) & (0x1 << 23)) && ((DRV_Reg32(HW_RESV) & (0x1 << 20)) == 0))
{
upmu_buck_vosel_dvs_11(BUCK_VPROC, 0x19); // P.K. DVS_VOL_11
}
else
{
if ((DRV_Reg32(HW_RESV) & (0x1 << 21)))
volt_bias = 2;
else if ((DRV_Reg32(HW_RESV) & (0x1 << 22)))
volt_bias = 1;
else
volt_bias = 0;
volt = (DRV_Reg32(HW_RESV) & 0xE000) >> 13;
if (volt == 0x0)
upmu_buck_vosel_dvs_11(BUCK_VPROC, (0x17 + volt_bias));
else if (volt == 0x1)
upmu_buck_vosel_dvs_11(BUCK_VPROC, (0x16 + volt_bias));
else if (volt == 0x2)
upmu_buck_vosel_dvs_11(BUCK_VPROC, (0x15 + volt_bias));
else if (volt == 0x3)
upmu_buck_vosel_dvs_11(BUCK_VPROC, (0x14 + volt_bias));
else if (volt == 0x4)
upmu_buck_vosel_dvs_11(BUCK_VPROC, (0x13 + volt_bias));
else if (volt == 0x5)
upmu_buck_vosel_dvs_11(BUCK_VPROC, (0x18 + volt_bias));
else if (volt == 0x6)
upmu_buck_vosel_dvs_11(BUCK_VPROC, (0x19 + volt_bias));
else if (volt == 0x7)
upmu_buck_vosel_dvs_11(BUCK_VPROC, (0x19 + volt_bias));
else
upmu_buck_vosel_dvs_11(BUCK_VPROC, (0x13 + volt_bias));
}
}
void mt6577_irq_set_sens(unsigned int irq, unsigned int sens)
{
unsigned long flags;
unsigned int config;
if (sens == MT65xx_EDGE_SENSITIVE) {
config = DRV_Reg32(GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4);
config |= (0x2 << (irq % 16) * 2);
DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4, config);
}else {
config = DRV_Reg32(GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4);
config &= ~(0x2 << (irq % 16) * 2);
DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4, config);
}
}
int gpt_check_irq(unsigned int id)
{
unsigned int mask = 0x1 << id;
unsigned int status = DRV_Reg32(GPT_IRQSTA);
return (status & mask) ? 1 : 0;
}
static void mtk_wdt_reset(char mode)
{
/* Watchdog Rest */
unsigned int wdt_mode_val;
DRV_WriteReg32(MTK_WDT_RESTART, MTK_WDT_RESTART_KEY);
wdt_mode_val = DRV_Reg32(MTK_WDT_MODE);
/* clear autorestart bit: autoretart: 1, bypass power key, 0: not bypass power key */
wdt_mode_val &=(~MTK_WDT_MODE_AUTO_RESTART);
/* make sure WDT mode is hw reboot mode, can not config isr mode */
wdt_mode_val &=(~(MTK_WDT_MODE_IRQ|MTK_WDT_MODE_ENABLE | MTK_WDT_MODE_DUAL_MODE));
wdt_mode_val &= ~MTK_WDT_MODE_DDRRSV_MODE;
if(mode) { /* mode != 0 means by pass power key reboot, We using auto_restart bit as by pass power key flag */
wdt_mode_val = wdt_mode_val | (MTK_WDT_MODE_KEY|MTK_WDT_MODE_EXTEN|MTK_WDT_MODE_AUTO_RESTART);
DRV_WriteReg32(MTK_WDT_MODE, wdt_mode_val);
} else {
wdt_mode_val = wdt_mode_val | (MTK_WDT_MODE_KEY|MTK_WDT_MODE_EXTEN);
DRV_WriteReg32(MTK_WDT_MODE,wdt_mode_val);
}
gpt_busy_wait_us(100);
DRV_WriteReg32(MTK_WDT_SWRST, MTK_WDT_SWRST_KEY);
}
int mt_cpu_ss_thread_handler(void *unused)
{
kal_uint32 flag = 0;
do {
ktime_t ktime = ktime_set(mt_cpu_ss_period_s, mt_cpu_ss_period_ns);
wait_event_interruptible(mt_cpu_ss_timer_waiter, mt_cpu_ss_timer_flag != 0);
mt_cpu_ss_timer_flag = 0;
if (!flag) {
mt_cpufreq_clock_switch(0, TOP_CKMUXSEL_CLKSQ);
flag = 1;
} else {
mt_cpufreq_clock_switch(0, TOP_CKMUXSEL_ARMPLL);
flag = 0;
}
if (mt_cpu_ss_debug_mode)
printk("[%s]: TOP_CKMUXSEL = 0x%x\n", __func__, DRV_Reg32(TOP_CKMUXSEL));
hrtimer_start(&mt_cpu_ss_timer, ktime, HRTIMER_MODE_REL);
} while (!kthread_should_stop());
return 0;
}
void drv_idc_set_baudrate(kal_uint32 baudrate)
{
kal_uint8 tmp_lcr = 0;
kal_uint32 freq_div = 1;
kal_uint32 sample_count = 0;
idc_port.DCB.u4Baud = baudrate;
if(baudrate)
{
do {
sample_count = (BUS_CLOCK + (freq_div * baudrate / 2)) / (freq_div * baudrate);
if(sample_count > 0xff) freq_div++;
} while(sample_count > 0xff);
}
// configure register
// based on sample_count * baud_pulse, baud_rate = system clock frequency / (SAMPLE_COUNT + 1) / {DLM, DLL}
DRV_WriteReg32(IDC_UART_RATE_STEP, ID_UART_RATE_STEP_COUNT);
tmp_lcr = DRV_Reg32(IDC_UART_LCR);
DRV_WriteReg32(IDC_UART_LCR, tmp_lcr | IDC_UART_LCR_DLAB);
// -- DLAB start --
DRV_WriteReg32(IDC_UART_DLL, freq_div & 0xFF);
DRV_WriteReg32(IDC_UART_DLM, (freq_div >> 8) & 0xFF);
DRV_WriteReg32(IDC_UART_STEP_COUNT, sample_count - 1);
DRV_WriteReg32(IDC_UART_SAMPLE_COUNT, sample_count >> 1);
DRV_WriteReg32(IDC_UART_LCR, tmp_lcr);
// -- DLAB end --
}
