void init_dsi(BOOL isDsiPoweredOn) { DSI_CHECK_RET(DSI_Init(isDsiPoweredOn)); DSI_CHECK_RET(DSI_TXRX_Control(TRUE, //cksm_en TRUE, //ecc_en lcm_params->dsi.LANE_NUM, //ecc_en 0, //vc_num FALSE, //null_packet_en FALSE, //err_correction_en FALSE, //dis_eotp_en 0)); //max_return_size //initialize DSI_PHY DSI_PHY_clk_switch(TRUE); DSI_PHY_TIMCONFIG(lcm_params); DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM); if(lcm_params->dsi.mode != CMD_MODE) { DSI_Config_VDO_Timing(lcm_params); DSI_CHECK_RET(DSI_PS_Control(lcm_params->dsi.PS, lcm_params->width * dsiTmpBufBpp)); } DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE)); }
void init_dsi(BOOL isDsiPoweredOn) { //xuecheng's workaround for 82 dsi video mode if (lcm_params->dsi.mode == CMD_MODE) { DSI_PHY_clk_setting(lcm_params); } // pr_debug("[DSI] %s, line:%d\n", __func__, __LINE__); DSI_CHECK_RET(DSI_Init(isDsiPoweredOn)); dsi_IsGlitchWorkaroundEnabled(); if(0 < lcm_params->dsi.compatibility_for_nvk) { DSI_CHECK_RET(DSI_TXRX_Control(TRUE, //cksm_en TRUE, //ecc_en lcm_params->dsi.LANE_NUM, //ecc_en 0, //vc_num FALSE, //null_packet_en FALSE, //err_correction_en FALSE, //dis_eotp_en FALSE, 0)); //max_return_size // DSI_set_noncont_clk(false,0); // DSI_Detect_glitch_enable(true); } else { DSI_CHECK_RET(DSI_TXRX_Control(TRUE, //cksm_en TRUE, //ecc_en lcm_params->dsi.LANE_NUM, //ecc_en 0, //vc_num FALSE, //null_packet_en FALSE, //err_correction_en FALSE, //dis_eotp_en (BOOL)(1 - lcm_params->dsi.cont_clock), 0)); //max_return_size } //initialize DSI_PHY DSI_PHY_clk_switch(TRUE); DSI_PHY_TIMCONFIG(lcm_params); DSI_CHECK_RET(DSI_PS_Control(lcm_params->dsi.PS, lcm_params->height, lcm_params->width * dsiTmpBufBpp)); if(lcm_params->dsi.mode != CMD_MODE) { DSI_Config_VDO_Timing(lcm_params); DSI_Set_VM_CMD(lcm_params); // if(0 < lcm_params->dsi.compatibility_for_nvk) // DSI_Config_VDO_FRM_Mode(); } DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE)); }
void init_dsi(BOOL isDsiPoweredOn) { DSI_CHECK_RET(DSI_Init(isDsiPoweredOn)); DSI_CHECK_RET(DSI_TXRX_Control(TRUE, //cksm_en TRUE, //ecc_en lcm_params->dsi.LANE_NUM, //ecc_en 0, //vc_num FALSE, //null_packet_en FALSE, //err_correction_en FALSE, //dis_eotp_en 0)); //max_return_size //initialize DSI_PHY #ifdef MT65XX_NEW_DISP DSI_PLL_Select(lcm_params->dsi.pll_select); #ifdef LVDS_SSC #if(LVDS_SSC) if((lcm_params->dsi.pll_select) && (lcm_params->dsi.mode != CMD_MODE)){ lcd_fps = lcd_fps * (100 - LVDS_SSC/2) / 100; printk("init_dsi: lcd_fps = %d\n", lcd_fps); } #endif #endif #endif DSI_PHY_clk_switch(TRUE); DSI_PHY_TIMCONFIG(lcm_params); #ifndef MT65XX_NEW_DISP DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM); #else if (lcm_params->dsi.mode == CMD_MODE) { DSI_PHY_clk_setting(lcm_params); } DSI_CHECK_RET(DSI_PS_Control(lcm_params->dsi.PS, lcm_params->height, lcm_params->width * dsiTmpBufBpp)); #endif if(lcm_params->dsi.mode != CMD_MODE) { DSI_Config_VDO_Timing(lcm_params); #ifndef MT65XX_NEW_DISP DSI_CHECK_RET(DSI_PS_Control(lcm_params->dsi.PS, lcm_params->width * dsiTmpBufBpp)); #endif } DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE)); }
void init_dsi(BOOL isDsiPoweredOn) { DSI_PHY_clk_setting(lcm_params); // DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "%s, line:%d\n", __func__, __LINE__); DSI_CHECK_RET(DSI_Init(isDsiPoweredOn)); //if(1 == lcm_params->dsi.compatibility_for_nvk){ if(0){ DSI_CHECK_RET(DSI_TXRX_Control(TRUE, //cksm_en TRUE, //ecc_en lcm_params->dsi.LANE_NUM, //ecc_en 0, //vc_num FALSE, //null_packet_en FALSE, //err_correction_en FALSE, //dis_eotp_en 0)); //max_return_size DSI_set_noncont_clk(false,0); } else { DSI_CHECK_RET(DSI_TXRX_Control(TRUE, //cksm_en TRUE, //ecc_en lcm_params->dsi.LANE_NUM, //ecc_en 0, //vc_num FALSE, //null_packet_en FALSE, //err_correction_en FALSE, //dis_eotp_en 0)); //max_return_size } //initialize DSI_PHY DSI_PHY_clk_switch(TRUE, lcm_params); DSI_PHY_TIMCONFIG(lcm_params); DSI_CHECK_RET(DSI_PS_Control(lcm_params->dsi.PS, lcm_params->height, lcm_params->width * dsiTmpBufBpp)); if(lcm_params->dsi.mode != CMD_MODE) { DSI_Config_VDO_Timing(lcm_params); DSI_Set_VM_CMD(lcm_params); //if(1 == lcm_params->dsi.compatibility_for_nvk) if(0) DSI_Config_VDO_FRM_Mode(); } DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE)); }
// protected by sem_early_suspend, sem_update_screen static DISP_STATUS dsi_enable_power(BOOL enable) { disp_drv_dsi_init_context(); if(lcm_params->dsi.mode == CMD_MODE) { if (enable) { #if 0 // Switch bus to MIPI TX. DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE)); DSI_PHY_clk_switch(TRUE, lcm_params); DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM); DSI_CHECK_RET(DSI_PowerOn()); DSI_WaitForNotBusy(); DSI_clk_HS_mode(0); DSI_clk_ULP_mode(0); DSI_lane0_ULP_mode(0); DSI_Reset(); LCD_CHECK_RET(LCD_PowerOn()); #else #ifndef MT65XX_NEW_DISP DSI_PHY_clk_switch(TRUE, lcm_params); DSI_CHECK_RET(DSI_PowerOn()); if(Need_Wait_ULPS()) Wait_ULPS_Mode(); DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM); #else // enable MMSYS CG DSI_CHECK_RET(DSI_PowerOn()); // initialize clock setting DSI_PHY_clk_setting(lcm_params); // initialize dsi timing DSI_PHY_TIMCONFIG(lcm_params); // restore dsi register DSI_CHECK_RET(DSI_RestoreRegisters()); // enable sleep-out mode DSI_CHECK_RET(DSI_SleepOut()); // enter HS mode DSI_PHY_clk_switch(TRUE, lcm_params); // enter wakeup DSI_CHECK_RET(DSI_Wakeup()); // enable clock DSI_CHECK_RET(DSI_EnableClk()); // engine reset DSI_Reset(); #endif DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE)); #ifndef MT65XX_NEW_DISP Wait_WakeUp(); #endif #endif } else { // backup dsi register DSI_CHECK_RET(DSI_WaitForEngineNotBusy()); DSI_CHECK_RET(DSI_BackupRegisters()); // enter ULPS mode DSI_clk_ULP_mode(1); DSI_lane0_ULP_mode(1); mdelay(1); // disable engine clock DSI_CHECK_RET(DSI_DisableClk()); // disable CG DSI_CHECK_RET(DSI_PowerOff()); // disable mipi pll DSI_PHY_clk_switch(FALSE, lcm_params); // Switch bus to GPIO, then power level will be decided by GPIO setting. DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE)); } } else { if (enable) { #if 0 // Switch bus to MIPI TX. DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE)); DSI_PHY_clk_switch(TRUE, lcm_params); DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM); DSI_CHECK_RET(DSI_PowerOn()); DSI_clk_ULP_mode(0); DSI_lane0_ULP_mode(0); DSI_clk_HS_mode(0); DSI_Reset(); DPI_CHECK_RET(DPI_PowerOn()); LCD_CHECK_RET(LCD_PowerOn()); #else #ifndef MT65XX_NEW_DISP DSI_PHY_clk_switch(TRUE, lcm_params); DSI_CHECK_RET(DSI_PowerOn()); if(Need_Wait_ULPS()) Wait_ULPS_Mode(); DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM); #else needStartDSI = true; // enable MMSYS CG DSI_CHECK_RET(DSI_PowerOn()); // initialize clock setting DSI_PHY_clk_setting(lcm_params); // initialize dsi timing DSI_PHY_TIMCONFIG(lcm_params); // restore dsi register DSI_CHECK_RET(DSI_RestoreRegisters()); // enable sleep-out mode DSI_CHECK_RET(DSI_SleepOut()); // enter HS mode DSI_PHY_clk_switch(TRUE, lcm_params); // enter wakeup DSI_CHECK_RET(DSI_Wakeup()); // enable clock DSI_CHECK_RET(DSI_EnableClk()); // engine reset DSI_Reset(); #endif DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE)); #ifndef MT65XX_NEW_DISP Wait_WakeUp(); #endif #endif } else { #ifndef BUILD_UBOOT is_video_mode_running = false; if(lcm_params->dsi.noncont_clock) DSI_set_noncont_clk(false, lcm_params->dsi.noncont_clock_period); if(lcm_params->dsi.lcm_int_te_monitor) DSI_set_int_TE(false, lcm_params->dsi.lcm_int_te_period); #endif // backup dsi register DSI_CHECK_RET(DSI_WaitForEngineNotBusy()); DSI_CHECK_RET(DSI_BackupRegisters()); // enter ULPS mode DSI_clk_ULP_mode(1); DSI_lane0_ULP_mode(1); mdelay(1); // disable engine clock DSI_CHECK_RET(DSI_DisableClk()); // disable CG DSI_CHECK_RET(DSI_PowerOff()); // disable mipi pll DSI_PHY_clk_switch(FALSE, lcm_params); // Switch bus to GPIO, then power level will be decided by GPIO setting. DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE)); } } return DISP_STATUS_OK; }