void dspi_slave_setup(uint32_t instance, uint32_t baudrate) { dspi_data_format_config_t config; uint32_t baseAddr = SPI0_BASE; // Enable clock CLOCK_SYS_EnableSpiClock(instance); // Clear flags DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiTxComplete); DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiTxAndRxStatus); DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiEndOfQueue); DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiTxFifoUnderflow); DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiTxFifoFillRequest); DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiRxFifoOverflow); DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiRxFifoDrainRequest); // Enable HAL DSPI_HAL_Init(baseAddr); DSPI_HAL_SetMasterSlaveMode(baseAddr, kDspiSlave); DSPI_HAL_Enable(baseAddr); // Disable transfer DSPI_HAL_StopTransfer(baseAddr); // PCS popularity DSPI_HAL_SetPcsPolarityMode(baseAddr, kDspiPcs0, kDspiPcs_ActiveLow); // CTAR DSPI_HAL_SetBaudRate(baseAddr, kDspiCtar0, baudrate, 72000000); config.bitsPerFrame = 16; config.clkPhase = kDspiClockPhase_FirstEdge; config.clkPolarity = kDspiClockPolarity_ActiveHigh; config.direction = kDspiMsbFirst; DSPI_HAL_SetDataFormat(baseAddr, kDspiCtar0, &config); // Interrupt INT_SYS_EnableIRQ(g_dspiIrqId[instance]); DSPI_HAL_SetIntMode(g_dspiBaseAddr[instance], kDspiTxFifoUnderflow, false); DSPI_HAL_SetIntMode(g_dspiBaseAddr[instance], kDspiTxFifoFillRequest, false); // DMA DSPI_HAL_SetTxFifoFillDmaIntMode(g_dspiBaseAddr[instance], kDspiGenerateIntReq, true); DSPI_HAL_SetRxFifoDrainDmaIntMode(g_dspiBaseAddr[instance], kDspiGenerateDmaReq, true); }
/*FUNCTION********************************************************************** * * Function Name : DSPI_DRV_DmaMasterTransferBlocking * Description : Performs a blocking SPI master mode transfer with DMA support. * * This function simultaneously sends and receives data on the SPI bus, as SPI is naturally * a full-duplex bus. The function does not return until the transfer is complete. * *END**************************************************************************/ dspi_status_t DSPI_DRV_DmaMasterTransferBlocking(uint32_t instance, const dspi_dma_device_t * device, const uint8_t * sendBuffer, uint8_t * receiveBuffer, size_t transferByteCount, uint32_t timeout) { /* instantiate local variable of type dspi_dma_master_state_t and point to global state */ dspi_dma_master_state_t * dspiDmaState = (dspi_dma_master_state_t *)g_dspiStatePtr[instance]; SPI_Type *base = g_dspiBase[instance]; dspi_status_t error = kStatus_DSPI_Success; /* If the transfer count is zero, then return immediately.*/ if (transferByteCount == 0) { return kStatus_DSPI_InvalidParameter; } dspiDmaState->isTransferBlocking = true; /* Indicates this is a blocking transfer */ /* As this is a synchronous transfer, set up the sync status variable*/ osa_status_t syncStatus; if (DSPI_DRV_DmaMasterStartTransfer(instance, device, sendBuffer, receiveBuffer, transferByteCount) == kStatus_DSPI_Busy) { return kStatus_DSPI_Busy; } /* As this is a synchronous transfer, wait until the transfer is complete.*/ do { syncStatus = OSA_SemaWait(&dspiDmaState->irqSync, timeout); } while(syncStatus == kStatus_OSA_Idle); /* If a timeout occurs, stop the transfer by setting the isTransferInProgress to false and * disabling DMA requests and interrupts, then return the timeout error status. */ if (syncStatus != kStatus_OSA_Success) { /* The transfer is complete.*/ dspiDmaState->isTransferInProgress = false; /* Disable the Receive FIFO Drain DMA Request */ DSPI_HAL_SetRxFifoDrainDmaIntMode(base, kDspiGenerateDmaReq, false); /* Disable TFFF DMA request */ DSPI_HAL_SetTxFifoFillDmaIntMode(base, kDspiGenerateDmaReq, false); /* Disable End of Queue request */ DSPI_HAL_SetIntMode(base, kDspiEndOfQueue, false); error = kStatus_DSPI_Timeout; } return error; }
/************************************************************************* * Function Name: SPI0_init * Parameters: none * Return: none * Description: SPI initialization *************************************************************************/ void SPI0_init(void) { dspi_baud_rate_divisors_t divisors; divisors.doubleBaudRate = 0; divisors.baudRateDivisor = 3; divisors.prescaleDivisor = 3; dspi_data_format_config_t config; config.clkPhase = kDspiClockPhase_SecondEdge; config.bitsPerFrame = 8; config.clkPolarity = kDspiClockPolarity_ActiveHigh; config.direction = kDspiMsbFirst; #if defined(KV10Z7_SERIES) PORT_HAL_SetMuxMode(PORTC_BASE_PTR,2,kPortMuxAsGpio);// MC33937 RESET GPIO_HAL_SetPinDir(GPIOC_BASE_PTR, 2, kGpioDigitalOutput); PORT_HAL_SetMuxMode(PORTD_BASE_PTR,7,kPortMuxAsGpio);// MC33937 DRV_EN GPIO_HAL_SetPinDir(GPIOD_BASE_PTR, 7, kGpioDigitalOutput); #elif (defined(KV10Z1287_SERIES) || defined(KV11Z7_SERIES)) PORT_HAL_SetMuxMode(PORTE_BASE_PTR,29,kPortMuxAsGpio);// MC33937 DRV_EN GPIO_HAL_SetPinDir(GPIOE_BASE_PTR, 29, kGpioDigitalOutput); #endif GPIO_HAL_SetPinOutput(GPIOC_BASE_PTR, 2);//MC33937_RESET_HIGH; #if defined(KV10Z7_SERIES) GPIO_HAL_SetPinOutput(GPIOD_BASE_PTR, 7);//MC33937_ENABLE_HIGH; #elif (defined(KV10Z1287_SERIES) || defined(KV11Z7_SERIES)) GPIO_HAL_SetPinOutput(GPIOE_BASE_PTR, 29); #endif DSPI_HAL_StopTransfer(SPI0_BASE_PTR);// halt SPI before SPI setting DSPI_HAL_Enable(SPI0_BASE_PTR);//Enables the DSPI peripheral and sets the MCR MDIS to 0. DSPI_HAL_SetMasterSlaveMode(SPI0_BASE_PTR, kDspiMaster);//Enable Master Mode DSPI_HAL_SetPcsPolarityMode(SPI0_BASE_PTR, kDspiPcs0,kDspiPcs_ActiveLow);//The setting for either "active high, inactive low (0)" or "active low, inactive high(1)" of type dspi_pcs_polarity_config_t. DSPI_HAL_SetFifoCmd(SPI0_BASE_PTR, false, false);//Disable the DSPI FIFOs. DSPI_HAL_PresetTransferCount(SPI0_BASE_PTR, 0x0000);//Pre-sets the transfer count. DSPI_HAL_SetDelay(SPI0_BASE_PTR, kDspiCtar0,3,0, kDspiPcsToSck); // CTAR0 selection option for master or slave mode DSPI_HAL_SetDelay(SPI0_BASE_PTR, kDspiCtar0,2,0, kDspiLastSckToPcs); DSPI_HAL_SetDelay(SPI0_BASE_PTR, kDspiCtar0,0,2, kDspiAfterTransfer); DSPI_HAL_SetBaudDivisors(SPI0_BASE_PTR, kDspiCtar0, &divisors); DSPI_HAL_SetDataFormat(SPI0_BASE_PTR, kDspiCtar0, &config); DSPI_HAL_ClearStatusFlag(SPI0_BASE_PTR ,kDspiTxComplete);///*!< TCF status/interrupt enable */ DSPI_HAL_ClearStatusFlag(SPI0_BASE_PTR ,kDspiEndOfQueue);///*!< EOQF status/interrupt enable*/ DSPI_HAL_ClearStatusFlag(SPI0_BASE_PTR ,kDspiTxFifoUnderflow);///*!< TFUF status/interrupt enable*/ DSPI_HAL_ClearStatusFlag(SPI0_BASE_PTR ,kDspiTxFifoFillRequest);///*!< TFFF status/interrupt enable*/ DSPI_HAL_ClearStatusFlag(SPI0_BASE_PTR ,kDspiRxFifoOverflow);///*!< RFOF status/interrupt enable*/ DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiTxComplete, false);/*!< TCF status/interrupt disable */ DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiEndOfQueue, false);/*!< EOQF status/interrupt disable */ DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiTxFifoUnderflow, false);/*!< TFUF status/interrupt disable*/ DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiTxFifoFillRequest, false);/*!< TFFF status/interrupt disable*/ DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiRxFifoOverflow, false);/*!< RFOF status/interrupt disable*/ DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiRxFifoDrainRequest, false);/*!< RFDF status/interrupt disable*/ DSPI_HAL_StartTransfer(SPI0_BASE_PTR);// Starts the DSPI transfers, clears HALT bit in MCR. PORT_HAL_SetMuxMode(PORTD_BASE_PTR, 3, kPortMuxAlt2); PORT_HAL_SetMuxMode(PORTD_BASE_PTR, 2, kPortMuxAlt2); PORT_HAL_SetMuxMode(PORTC_BASE_PTR, 0, kPortMuxAlt7); PORT_HAL_SetMuxMode(PORTC_BASE_PTR, 5, kPortMuxAlt2); }