int parse_decon_mic_dt_exynos5430(struct device_node *np)
{
u32 temp;
DT_READ_U32_OPTIONAL(np, "sysreg1", g_mic_config.sysreg1);
DT_READ_U32_OPTIONAL(np, "sysreg2", g_mic_config.sysreg2);
return 0;
}
static int parse_fb_win_variant(struct device_node *np, char *node_name,
struct s3c_fb_win_variant *pvar)
{
u32 temp;
int ret = 0;
struct device_node *np_fbwin;
np_fbwin = of_find_node_by_name(np, node_name);
if (!np_fbwin) {
pr_err("%s: could not find fb_win_variant node\n",
node_name);
return -EINVAL;
}
DT_READ_U32_OPTIONAL(np_fbwin, "has_osd_c", pvar->has_osd_c);
DT_READ_U32_OPTIONAL(np_fbwin, "has_osd_d", pvar->has_osd_d);
DT_READ_U32_OPTIONAL(np_fbwin, "has_osd_alpha", pvar->has_osd_alpha);
DT_READ_U32_OPTIONAL(np_fbwin, "osd_size_off", pvar->osd_size_off);
DT_READ_U32_OPTIONAL(np_fbwin, "palette_size", pvar->palette_sz);
DT_READ_U32_SETBITS(np_fbwin, "VALID_BPP_1248",
pvar->valid_bpp, VALID_BPP1248);
DT_READ_U32_SETBITS(np_fbwin, "VALID_BPP_13",
pvar->valid_bpp, VALID_BPP(13));
DT_READ_U32_SETBITS(np_fbwin, "VALID_BPP_15",
pvar->valid_bpp, VALID_BPP(15));
DT_READ_U32_SETBITS(np_fbwin, "VALID_BPP_16",
pvar->valid_bpp, VALID_BPP(16));
DT_READ_U32_SETBITS(np_fbwin, "VALID_BPP_18",
pvar->valid_bpp, VALID_BPP(18));
DT_READ_U32_SETBITS(np_fbwin, "VALID_BPP_19",
pvar->valid_bpp, VALID_BPP(19));
DT_READ_U32_SETBITS(np_fbwin, "VALID_BPP_24",
pvar->valid_bpp, VALID_BPP(24));
DT_READ_U32_SETBITS(np_fbwin, "VALID_BPP_25",
pvar->valid_bpp, VALID_BPP(25));
DT_READ_U32_SETBITS(np_fbwin, "VALID_BPP_32",
pvar->valid_bpp, VALID_BPP(32));
return ret;
}
int parse_lcd_drvdata(struct device_node *np)
{
int ret;
u32 temp, res[3];
struct device_node *node;
node = of_parse_phandle(np, "lcd_info", 0);
DT_READ_U32_OPTIONAL(node, "mode", g_decon_lcd.mode);
DT_READ_U32_OPTIONAL(node, "mode", g_dsim_config.e_interface);
ret = of_property_read_u32_array(node, "resolution", res, 2);
g_decon_lcd.xres = res[0];
g_decon_lcd.yres = res[1];
ret = of_property_read_u32_array(node, "size", res, 2);
g_decon_lcd.width = res[0];
g_decon_lcd.height = res[1];
DT_READ_U32_OPTIONAL(node, "timing,refresh", g_decon_lcd.fps);
ret = of_property_read_u32_array(node, "timing,h-porch", res, 3);
g_decon_lcd.hbp = res[0];
g_decon_lcd.hfp = res[1];
g_decon_lcd.hsa = res[2];
ret = of_property_read_u32_array(node, "timing,v-porch", res, 3);
g_decon_lcd.vbp = res[0];
g_decon_lcd.vfp = res[1];
g_decon_lcd.vsa = res[2];
DT_READ_U32_OPTIONAL(node, "timing,dsi-hs-clk", g_decon_lcd.hs_clk);
DT_READ_U32_OPTIONAL(node, "timing,dsi-escape-clk", g_decon_lcd.esc_clk);
DT_READ_U32_OPTIONAL(node, "mic", g_decon_lcd.mic);
return ret;
}
static int parse_dsi_drvdata(struct device_node *np)
{
u32 temp, i;
DT_READ_U32_OPTIONAL(np, "e_interface", g_dsim_config.e_interface);
DT_READ_U32_OPTIONAL(np, "e_pixel_format",
g_dsim_config.e_pixel_format);
DT_READ_U32_OPTIONAL(np, "auto_flush", g_dsim_config.auto_flush);
DT_READ_U32_OPTIONAL(np, "eot_disable", g_dsim_config.eot_disable);
DT_READ_U32_OPTIONAL(np, "auto_vertical_cnt",
g_dsim_config.auto_vertical_cnt);
DT_READ_U32_OPTIONAL(np, "hse", g_dsim_config.hse);
DT_READ_U32_OPTIONAL(np, "hfp", g_dsim_config.hfp);
DT_READ_U32_OPTIONAL(np, "hbp", g_dsim_config.hbp);
DT_READ_U32_OPTIONAL(np, "hsa", g_dsim_config.hsa);
DT_READ_U32_OPTIONAL(np, "e_no_data_lane",
g_dsim_config.e_no_data_lane);
DT_READ_U32_OPTIONAL(np, "e_byte_clk", g_dsim_config.e_byte_clk);
DT_READ_U32_OPTIONAL(np, "e_burst_mode", g_dsim_config.e_burst_mode);
DT_READ_U32_OPTIONAL(np, "p", g_dsim_config.p);
DT_READ_U32_OPTIONAL(np, "m", g_dsim_config.m);
DT_READ_U32_OPTIONAL(np, "s", g_dsim_config.s);
DT_READ_U32_OPTIONAL(np, "pll_stable_time",
g_dsim_config.pll_stable_time);
DT_READ_U32_OPTIONAL(np, "esc_clk", g_dsim_config.esc_clk);
DT_READ_U32_OPTIONAL(np, "stop_holding_cnt",
g_dsim_config.stop_holding_cnt);
DT_READ_U32_OPTIONAL(np, "bta_timeout", g_dsim_config.bta_timeout);
DT_READ_U32_OPTIONAL(np, "rx_timeout", g_dsim_config.rx_timeout);
for (i = 0; i < of_gpio_count(np); i++)
g_disp_gpios.id[i] = of_get_gpio(np, i);
return 0;
}
