/**
* Show the whether core is hibernated or not.
*/
static ssize_t rem_wakeup_pwrdn_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifndef DWC_HOST_ONLY
dwc_otg_device_t *otg_dev = get_otg_dev();
if (dwc_otg_get_core_state(otg_dev->core_if)) {
DWC_PRINTF("Core is in hibernation\n");
} else {
DWC_PRINTF("Core is not in hibernation\n");
}
#endif /* DWC_HOST_ONLY */
return 0;
}
/* This function prints out a buffer in the format described in the Association
* Model specification. */
static void dh_dump(char *str, void *_num, int len)
{
uint8_t *num = _num;
int i;
DWC_PRINTF("%s\n", str);
for (i = 0; i < len; i ++) {
DWC_PRINTF("%02x", num[i]);
if (((i + 1) % 2) == 0) DWC_PRINTF(" ");
if (((i + 1) % 26) == 0) DWC_PRINTF("\n");
}
DWC_PRINTF("\n");
}
/**
* Show the whether core is hibernated or not.
*/
static ssize_t rem_wakeup_pwrdn_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifndef DWC_HOST_ONLY
struct platform_device *lm_dev
= container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(lm_dev);
if (dwc_otg_get_core_state(otg_dev->core_if))
DWC_PRINTF("Core is in hibernation\n");
else
DWC_PRINTF("Core is not in hibernation\n");
#endif /* DWC_HOST_ONLY */
return 0;
}
/**
* This function is used to submit an ISOC Transfer Request to an EP.
*
* - Every time a sync period completes the request's completion callback
* is called to provide data to the gadget driver.
* - Once submitted the request cannot be modified.
* - Each request is turned into periodic data packets untill ISO
* Transfer is stopped..
*/
static int iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req,
gfp_t gfp_flags)
{
int retval = 0;
if (!req || !req->process_buffer || !req->buf0 || !req->buf1) {
DWC_WARN("bad params\n");
return -EINVAL;
}
if (!usb_ep) {
DWC_PRINTF("bad params\n");
return -EINVAL;
}
req->status = -EINPROGRESS;
retval =
dwc_otg_pcd_iso_ep_start(gadget_wrapper->pcd, usb_ep, req->buf0,
req->buf1, req->dma0, req->dma1,
req->sync_frame, req->data_pattern_frame,
req->data_per_frame,
req->flags & USB_REQ_ISO_ASAP ? -1 : req->
start_frame, req->buf_proc_intrvl, req,
gfp_flags == GFP_ATOMIC ? 1 : 0);
if (retval) {
return -EINVAL;
}
return retval;
}
/**
* Dump global registers and either host or device registers (depending on the
* current mode of the core).
*/
static ssize_t regdump_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
dwc_otg_device_t *otg_dev = get_otg_dev();
DWC_PRINTF("otg_dev:%p\n", otg_dev);
DWC_PRINTF("core_if:%p\n", otg_dev->core_if);
dwc_otg_dump_global_registers(otg_dev->core_if);
if (dwc_otg_is_host_mode(otg_dev->core_if)) {
dwc_otg_dump_host_registers(otg_dev->core_if);
} else {
dwc_otg_dump_dev_registers(otg_dev->core_if);
}
return sprintf(buf, "Register Dump\n");
}
static void dump_urb_info(struct urb *urb, char *fn_name)
{
DWC_PRINTF("%s, urb %p\n", fn_name, urb);
DWC_PRINTF(" Device address: %d\n", usb_pipedevice(urb->pipe));
DWC_PRINTF(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
(usb_pipein(urb->pipe) ? "IN" : "OUT"));
DWC_PRINTF(" Endpoint type: %s\n", ( {
char *pipetype;
switch (usb_pipetype(urb->pipe)) {
case PIPE_CONTROL:
pipetype = "CONTROL"; break; case PIPE_BULK:
pipetype = "BULK"; break; case PIPE_INTERRUPT:
pipetype = "INTERRUPT"; break; case PIPE_ISOCHRONOUS:
pipetype = "ISOCHRONOUS"; break; default:
pipetype = "UNKNOWN"; break;};
pipetype;}
)) ;
static void adp_sense_timeout(void *ptr)
{
dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
core_if->adp.sense_timer_started = 0;
DWC_PRINTF("ADP SENSE TIMEOUT\n");
if (core_if->adp_enable) {
dwc_otg_adp_sense_stop(core_if);
dwc_otg_adp_probe_start(core_if);
}
}
static void adp_sense_timeout(void *ptr)
{
dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
core_if->adp.sense_timer_started = 0;
DWC_PRINTF("ADP SENSE TIMEOUT\n");
if (core_if->adp_enable) {
dwc_otg_adp_sense_stop(core_if);
DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg, adp_probe_func,
core_if, 2500, "start probe");
}
}
void dwc_run_dh_test_vectors(void)
{
uint8_t pkd[384];
uint8_t pkh[384];
uint8_t hashd[32];
uint8_t hashh[32];
uint8_t ck[16];
uint8_t kdk[32];
char dd[5];
DWC_PRINTF("\n\n\nDH_TEST_VECTORS\n\n");
/* compute the PKd and SHA-256(PKd || Nd) */
DWC_PRINTF("Computing PKd\n");
dwc_dh_pk(2, dh_a, pkd, hashd);
/* compute the PKd and SHA-256(PKh || Nd) */
DWC_PRINTF("Computing PKh\n");
dwc_dh_pk(2, dh_b, pkh, hashh);
/* compute the dhkey */
dwc_dh_derive_keys(2, pkh, pkd, dh_a, 0, dd, ck, kdk);
}
static ssize_t disconnect_us(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifndef DWC_HOST_ONLY
dwc_otg_device_t *otg_dev = get_otg_dev();
uint32_t val = simple_strtoul(buf, NULL, 16);
DWC_PRINTF("The Passed value is %04x\n", val);
dwc_otg_pcd_disconnect_us(otg_dev->pcd, 50);
#endif /* DWC_HOST_ONLY */
return count;
}
/**
* Store the sleep_status attribure.
*/
static ssize_t sleepstatus_store(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
dwc_otg_core_if_t *core_if = otg_dev->core_if;
if (dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)) {
if (dwc_otg_is_host_mode(core_if)) {
DWC_PRINTF("Host initiated resume\n");
dwc_otg_set_prtresume(otg_dev->core_if, 1);
}
}
return count;
}
/**
* Stops the ADP Probing
*
* @param core_if the pointer to core_if strucure.
*/
uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if)
{
adpctl_data_t adpctl;
DWC_PRINTF("Stop ADP probe\n");
core_if->adp.probe_enabled = 0;
core_if->adp.probe_counter = 0;
adpctl.d32 = dwc_otg_adp_read_reg(core_if);
adpctl.b.adpen = 0;
adpctl.b.adp_prb_int = 1;
adpctl.b.adp_tmout_int = 1;
adpctl.b.adp_sns_int = 1;
dwc_otg_adp_write_reg(core_if, adpctl.d32);
return 0;
}
static int _isoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
void *req_handle, int proc_buf_num)
{
int i, packet_count;
struct usb_gadget_iso_packet_descriptor *iso_packet = 0;
struct usb_iso_request *iso_req = req_handle;
if (proc_buf_num) {
iso_packet = iso_req->iso_packet_desc1;
} else {
iso_packet = iso_req->iso_packet_desc0;
}
packet_count =
dwc_otg_pcd_get_iso_packet_count(pcd, ep_handle, req_handle);
for (i = 0; i < packet_count; ++i) {
int status;
int actual;
int offset;
dwc_otg_pcd_get_iso_packet_params(pcd, ep_handle, req_handle,
i, &status, &actual, &offset);
switch (status) {
case -DWC_E_NO_DATA:
status = -ENODATA;
break;
default:
if (status) {
DWC_PRINTF("unknown status in isoc packet\n");
}
}
iso_packet[i].status = status;
iso_packet[i].offset = offset;
iso_packet[i].actual_length = actual;
}
iso_req->status = 0;
iso_req->process_buffer(ep_handle, iso_req);
return 0;
}
void w_conn_id_status_change(void *p)
{
dwc_otg_core_if_t *core_if = p;
uint32_t count = 0;
gotgctl_data_t gotgctl = {.d32 = 0 };
gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
/* B-Device connector (Device Mode) */
if (gotgctl.b.conidsts) {
/* Wait for switch to device mode. */
while (!dwc_otg_is_device_mode(core_if)) {
DWC_PRINTF("Waiting for Peripheral Mode, Mode=%s\n",
(dwc_otg_is_host_mode(core_if) ? "Host" :
"Peripheral"));
dwc_mdelay(100);
if (++count > 10000)
break;
}
DWC_ASSERT(++count < 10000,
"Connection id status change timed out");
#ifdef CONFIG_USB_OTG_UTILS
if (core_if->xceiver->otg->set_vbus)
core_if->xceiver->otg->set_vbus(core_if->xceiver->otg, false);
#endif
core_if->op_state = B_PERIPHERAL;
dwc_otg_core_init(core_if);
dwc_otg_enable_global_interrupts(core_if);
cil_pcd_start(core_if);
} else {
/* A-Device connector (Host Mode) */
while (!dwc_otg_is_host_mode(core_if)) {
DWC_PRINTF("Waiting for Host Mode, Mode=%s\n",
(dwc_otg_is_host_mode(core_if) ? "Host" :
"Peripheral"));
dwc_mdelay(100);
if (++count > 10000)
break;
}
DWC_ASSERT(++count < 10000,
"Connection id status change timed out");
core_if->op_state = A_HOST;
/*
* Initialize the Core for Host mode.
*/
dwc_otg_core_init(core_if);
dwc_otg_enable_global_interrupts(core_if);
cil_hcd_start(core_if);
}
}
/**
* This function handles the Connector ID Status Change Interrupt. It
* reads the OTG Interrupt Register (GOTCTL) to determine whether this
* is a Device to Host Mode transition or a Host Mode to Device
* Transition.
*
* This only occurs when the cable is connected/removed from the PHY
* connector.
*
* @param core_if Programming view of DWC_otg controller.
*/
int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t *core_if)
{
/*
* Need to disable SOF interrupt immediately. If switching from device
* to host, the PCD interrupt handler won't handle the interrupt if
* host mode is already set. The HCD interrupt handler won't get
* called if the HCD state is HALT. This means that the interrupt does
* not get handled and Linux complains loudly.
*/
gintmsk_data_t gintmsk = {.d32 = 0 };
gintsts_data_t gintsts = {.d32 = 0 };
gintmsk.b.sofintr = 1;
dwc_modify_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
DWC_DEBUGPL(DBG_CIL,
" ++Connector ID Status Change Interrupt++ (%s)\n",
(dwc_otg_is_host_mode(core_if) ? "Host" : "Device"));
/*
* Need to schedule a work, as there are possible DELAY function calls
*/
DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change,
core_if, "connection id status change");
/* Set flag and clear interrupt */
gintsts.b.conidstschng = 1;
dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/**
* This interrupt indicates that a device is initiating the Session
* Request Protocol to request the host to turn on bus power so a new
* session can begin. The handler responds by turning on bus power. If
* the DWC_otg controller is in low power mode, the handler brings the
* controller out of low power mode before turning on bus power.
*
* @param core_if Programming view of DWC_otg controller.
*/
int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t *core_if)
{
hprt0_data_t hprt0;
gintsts_data_t gintsts;
#ifndef DWC_HOST_ONLY
DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
if (dwc_otg_is_device_mode(core_if)) {
DWC_PRINTF("SRP: Device mode\n");
} else {
DWC_PRINTF("SRP: Host mode\n");
/* Turn on the port power bit. */
hprt0.d32 = dwc_otg_read_hprt0(core_if);
hprt0.b.prtpwr = 1;
dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
#ifdef CONFIG_USB_OTG
if (core_if->core_params->otg_supp_enable) {
/* Schedule a work item to init the core */
DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_init_core,
core_if, "SRP detected");
} else
#endif
{
/* Start the Connection timer. So a message can be displayed
* if connect does not occur within connection wait timeout */
cil_hcd_session_start(core_if);
}
}
#endif
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.sessreqintr = 1;
dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
void w_wakeup_detected(void *p)
{
dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *)p;
/*
* Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
* so that OPT tests pass with all PHYs).
*/
hprt0_data_t hprt0 = {.d32 = 0 };
#if 0
pcgcctl_data_t pcgcctl = {.d32 = 0 };
/* Restart the Phy Clock */
pcgcctl.b.stoppclk = 1;
dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0);
dwc_udelay(10);
#endif /*0 */
hprt0.d32 = dwc_otg_read_hprt0(core_if);
DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32);
/* dwc_mdelay(70); */
hprt0.b.prtres = 0; /* Resume */
dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n",
dwc_read_reg32(core_if->host_if->hprt0));
cil_hcd_resume(core_if);
/** Change to L0 state*/
core_if->lx_state = DWC_OTG_L0;
}
void w_a_periph_done(void *p)
{
dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *)p;
if (core_if->op_state == A_PERIPHERAL) {
/* Clear the a_peripheral flag, back to a_host. */
cil_pcd_stop(core_if);
cil_hcd_start(core_if);
core_if->op_state = A_HOST;
}
}
void w_peri_suspend_powersaving(void *p)
{
dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *)p;
if (core_if) {
/* Clear DWC Core interrupts before PHY suspend,
this is because to prevent DWC core Hangs while
accessing some registers with PHY suspended if at
all we get some core interrupts when phy in suspend*/
/* Clear any pending OTG Interrupts */
dwc_write_reg32(&core_if->core_global_regs->gotgint, 0xFFFFFFFF);
/* Clear any pending interrupts */
dwc_write_reg32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
dwc_otg_disable_global_interrupts(core_if);
/* Suspend trasceiver */
usb_phy_set_suspend(core_if->xceiver, 1);
}
}
/**
* This function is called when the ADP vbus timer expires. Timeout is 1.1s.
*/
static void adp_vbuson_timeout(void *ptr)
{
gpwrdn_data_t gpwrdn;
dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
hprt0_data_t hprt0 = {.d32 = 0 };
pcgcctl_data_t pcgcctl = {.d32 = 0 };
DWC_PRINTF("%s: 1.1 seconds expire after turning on VBUS\n",__FUNCTION__);
if (core_if) {
core_if->adp.vbuson_timer_started = 0;
/* Turn off vbus */
hprt0.b.prtpwr = 1;
DWC_MODIFY_REG32(core_if->host_if->hprt0, hprt0.d32, 0);
gpwrdn.d32 = 0;
/* Power off the core */
if (core_if->power_down == 2) {
/* Enable Wakeup Logic */
/* gpwrdn.b.wkupactiv = 1; */
gpwrdn.b.pmuactv = 0;
gpwrdn.b.pwrdnrstn = 1;
gpwrdn.b.pwrdnclmp = 1;
DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
gpwrdn.d32);
/* Suspend the Phy Clock */
pcgcctl.b.stoppclk = 1;
DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
/* Switch on VDD */
/* gpwrdn.b.wkupactiv = 1;*/
gpwrdn.b.pmuactv = 1;
gpwrdn.b.pwrdnrstn = 1;
gpwrdn.b.pwrdnclmp = 1;
DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
gpwrdn.d32);
} else {
/* Enable Power Down Logic */
gpwrdn.b.pmuintsel = 1;
gpwrdn.b.pmuactv = 1;
DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
}
/* Power off the core */
if (core_if->power_down == 2) {
gpwrdn.d32 = 0;
gpwrdn.b.pwrdnswtch = 1;
DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn,
gpwrdn.d32, 0);
}
/* Unmask SRP detected interrupt from Power Down Logic */
gpwrdn.d32 = 0;
gpwrdn.b.srp_det_msk = 1;
DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
dwc_otg_adp_probe_start(core_if);
dwc_otg_dump_global_registers(core_if);
dwc_otg_dump_host_registers(core_if);
}
}
/**
* Start the ADP Initial Probe timer to detect if Port Connected interrupt is
* not asserted within 1.1 seconds.
*
* @param core_if the pointer to core_if strucure.
*/
void dwc_otg_adp_vbuson_timer_start(dwc_otg_core_if_t * core_if)
{
core_if->adp.vbuson_timer_started = 1;
if (core_if->adp.vbuson_timer)
{
DWC_PRINTF("SCHEDULING VBUSON TIMER\n");
/* 1.1 secs + 60ms necessary for cil_hcd_start*/
DWC_TIMER_SCHEDULE(core_if->adp.vbuson_timer, 1160);
} else {
DWC_WARN("VBUSON_TIMER = %p\n",core_if->adp.vbuson_timer);
}
}
#if 0
/**
* Masks all DWC OTG core interrupts
*
*/
static void mask_all_interrupts(dwc_otg_core_if_t * core_if)
{
int i;
gahbcfg_data_t ahbcfg = {.d32 = 0 };
/* Mask Host Interrupts */
/* Clear and disable HCINTs */
for (i = 0; i < core_if->core_params->host_channels; i++) {
DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk, 0);
DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcint, 0xFFFFFFFF);
}
/* Clear and disable HAINT */
DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk, 0x0000);
DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haint, 0xFFFFFFFF);
/* Mask Device Interrupts */
if (!core_if->multiproc_int_enable) {
/* Clear and disable IN Endpoint interrupts */
DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, 0);
for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
diepint, 0xFFFFFFFF);
}
/* Clear and disable OUT Endpoint interrupts */
DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, 0);
for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
doepint, 0xFFFFFFFF);
}
/* Clear and disable DAINT */
DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daint,
0xFFFFFFFF);
DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, 0);
} else {
for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
diepeachintmsk[i], 0);
DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
diepint, 0xFFFFFFFF);
}
for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
doepeachintmsk[i], 0);
DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
doepint, 0xFFFFFFFF);
}
DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
0);
DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachint,
0xFFFFFFFF);
}
/* Disable interrupts */
ahbcfg.b.glblintrmsk = 1;
DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
/* Disable all interrupts. */
DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
/* Clear any pending interrupts */
DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
/* Clear any pending OTG Interrupts */
DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, 0xFFFFFFFF);
}
/**
* Unmask Port Connection Detected interrupt
*
*/
static void unmask_conn_det_intr(dwc_otg_core_if_t * core_if)
{
gintmsk_data_t gintmsk = {.d32 = 0,.b.portintr = 1 };
DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
}
#endif
/**
* Starts the ADP Probing
*
* @param core_if the pointer to core_if structure.
*/
uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if)
{
adpctl_data_t adpctl = {.d32 = 0};
gpwrdn_data_t gpwrdn;
#if 0
adpctl_data_t adpctl_int = {.d32 = 0, .b.adp_prb_int = 1,
.b.adp_sns_int = 1, b.adp_tmout_int};
#endif
dwc_otg_disable_global_interrupts(core_if);
DWC_PRINTF("ADP Probe Start\n");
core_if->adp.probe_enabled = 1;
adpctl.b.adpres = 1;
dwc_otg_adp_write_reg(core_if, adpctl.d32);
while (adpctl.b.adpres) {
adpctl.d32 = dwc_otg_adp_read_reg(core_if);
}
adpctl.d32 = 0;
gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
/* In Host mode unmask SRP detected interrupt */
gpwrdn.d32 = 0;
gpwrdn.b.sts_chngint_msk = 1;
if (!gpwrdn.b.idsts) {
gpwrdn.b.srp_det_msk = 1;
}
DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
adpctl.b.adp_tmout_int_msk = 1;
adpctl.b.adp_prb_int_msk = 1;
adpctl.b.prb_dschg = 1;
adpctl.b.prb_delta = 1;
adpctl.b.prb_per = 1;
adpctl.b.adpen = 1;
adpctl.b.enaprb = 1;
dwc_otg_adp_write_reg(core_if, adpctl.d32);
DWC_PRINTF("ADP Probe Finish\n");
return 0;
}
/**
* Starts the ADP Sense timer to detect if ADP Sense interrupt is not asserted
* within 3 seconds.
*
* @param core_if the pointer to core_if strucure.
*/
void dwc_otg_adp_sense_timer_start(dwc_otg_core_if_t * core_if)
{
core_if->adp.sense_timer_started = 1;
DWC_TIMER_SCHEDULE(core_if->adp.sense_timer, 3000 /* 3 secs */ );
}
/**
* Starts the ADP Sense
*
* @param core_if the pointer to core_if strucure.
*/
uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if)
{
adpctl_data_t adpctl;
DWC_PRINTF("ADP Sense Start\n");
/* Unmask ADP sense interrupt and mask all other from the core */
adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
adpctl.b.adp_sns_int_msk = 1;
dwc_otg_adp_write_reg(core_if, adpctl.d32);
dwc_otg_disable_global_interrupts(core_if); // vahrama
/* Set ADP reset bit*/
adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
adpctl.b.adpres = 1;
dwc_otg_adp_write_reg(core_if, adpctl.d32);
while (adpctl.b.adpres) {
adpctl.d32 = dwc_otg_adp_read_reg(core_if);
}
adpctl.b.adpres = 0;
adpctl.b.adpen = 1;
adpctl.b.enasns = 1;
dwc_otg_adp_write_reg(core_if, adpctl.d32);
dwc_otg_adp_sense_timer_start(core_if);
return 0;
}
/**
* Set the register offset for the next Register Access Read/Write
*/
static ssize_t regoffset_store(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
uint32_t offset = simple_strtoul(buf, NULL, 16);
#if defined(PCI_INTERFACE)
if (offset < 0x00040000) {
#else
if (offset < SZ_256K) {
#endif
otg_dev->reg_offset = offset;
} else {
dev_err(_dev, "invalid offset\n");
}
return count;
}
DEVICE_ATTR(regoffset, S_IRUGO | S_IWUSR, regoffset_show, regoffset_store);
/**
* Show the value of the register at the offset in the reg_offset
* attribute.
*/
static ssize_t regvalue_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
uint32_t val;
volatile uint32_t *addr;
if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
/* Calculate the address */
addr = (uint32_t *)(otg_dev->reg_offset +
(uint8_t *)otg_dev->base);
val = dwc_read_reg32(addr);
return snprintf(buf,
sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n") + 1,
"Reg@0x%06x = 0x%08x\n", otg_dev->reg_offset,
val);
} else {
dev_err(_dev, "Invalid offset (0x%0x)\n", otg_dev->reg_offset);
return sprintf(buf, "invalid offset\n");
}
}
/**
* Store the value in the register at the offset in the reg_offset
* attribute.
*
*/
static ssize_t regvalue_store(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
volatile uint32_t *addr;
uint32_t val = simple_strtoul(buf, NULL, 16);
/* dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val); */
if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
/* Calculate the address */
addr = (uint32_t *)(otg_dev->reg_offset +
(uint8_t *)otg_dev->base);
dwc_write_reg32(addr, val);
} else {
dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
otg_dev->reg_offset);
}
return count;
}
DEVICE_ATTR(regvalue, S_IRUGO | S_IWUSR, regvalue_show, regvalue_store);
/*
* Attributes
*/
DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode, "Mode");
DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable, "HNPCapable");
DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable, "SRPCapable");
DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hsic_connect, "HSIC Connect");
DWC_OTG_DEVICE_ATTR_BITFIELD_RW(inv_sel_hsic, "Invert Select HSIC");
/* DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode"); */
/* DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode"); */
DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected, "Bus Connected");
DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl, 0, "GOTGCTL");
DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,
&(otg_dev->core_if->core_global_regs->gusbcfg),
"GUSBCFG");
DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,
&(otg_dev->core_if->core_global_regs->grxfsiz),
"GRXFSIZ");
DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,
&(otg_dev->core_if->core_global_regs->gnptxfsiz),
"GNPTXFSIZ");
DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,
&(otg_dev->core_if->core_global_regs->gpvndctl),
"GPVNDCTL");
DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,
&(otg_dev->core_if->core_global_regs->ggpio),
"GGPIO");
DWC_OTG_DEVICE_ATTR_REG32_RW(guid, &(otg_dev->core_if->core_global_regs->guid),
"GUID");
DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,
&(otg_dev->core_if->core_global_regs->gsnpsid),
"GSNPSID");
DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed, "Device Speed");
DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed, "Device Enumeration Speed");
DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,
&(otg_dev->core_if->core_global_regs->hptxfsiz),
"HPTXFSIZ");
DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0, otg_dev->core_if->host_if->hprt0, "HPRT0");
/**
* @todo Add code to initiate the HNP.
*/
/**
* Show the HNP status bit
*/
static ssize_t hnp_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
return sprintf(buf, "HstNegScs = 0x%x\n",
dwc_otg_get_hnpstatus(otg_dev->core_if));
}
/**
* Set the HNP Request bit
*/
static ssize_t hnp_store(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
uint32_t in = simple_strtoul(buf, NULL, 16);
dwc_otg_set_hnpreq(otg_dev->core_if, in);
return count;
}
DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
/**
* @todo Add code to initiate the SRP.
*/
/**
* Show the SRP status bit
*/
static ssize_t srp_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifndef DWC_HOST_ONLY
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
return sprintf(buf, "SesReqScs = 0x%x\n",
dwc_otg_get_srpstatus(otg_dev->core_if));
#else
return sprintf(buf, "Host Only Mode!\n");
#endif
}
/**
* Set the SRP Request bit
*/
static ssize_t srp_store(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifndef DWC_HOST_ONLY
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
if (NULL != otg_dev->pcd)
dwc_otg_pcd_initiate_srp(otg_dev->pcd);
#endif
return count;
}
DEVICE_ATTR(srp, 0644, srp_show, srp_store);
/**
* @todo Need to do more for power on/off?
*/
/**
* Show the Bus Power status
*/
static ssize_t buspower_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
return sprintf(buf, "Bus Power = 0x%x\n",
dwc_otg_get_prtpower(otg_dev->core_if));
}
/**
* Set the Bus Power status
*/
static ssize_t buspower_store(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
uint32_t on = simple_strtoul(buf, NULL, 16);
dwc_otg_set_prtpower(otg_dev->core_if, on);
return count;
}
DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
/**
* @todo Need to do more for suspend?
*/
/**
* Show the Bus Suspend status
*/
static ssize_t bussuspend_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
return sprintf(buf, "Bus Suspend = 0x%x\n",
dwc_otg_get_prtsuspend(otg_dev->core_if));
}
/**
* Set the Bus Suspend status
*/
static ssize_t bussuspend_store(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
uint32_t in = simple_strtoul(buf, NULL, 16);
dwc_otg_set_prtsuspend(otg_dev->core_if, in);
return count;
}
DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
/**
* Show the status of Remote Wakeup.
*/
static ssize_t remote_wakeup_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifndef DWC_HOST_ONLY
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
return sprintf(buf,
"Remote Wakeup Sig = %d Enabled = %d LPM Remote Wakeup = %d\n",
dwc_otg_get_remotewakesig(otg_dev->core_if),
dwc_otg_pcd_get_rmwkup_enable(otg_dev->pcd),
dwc_otg_get_lpm_remotewakeenabled(otg_dev->core_if));
#else
return sprintf(buf, "Host Only Mode!\n");
#endif /* DWC_HOST_ONLY */
}
/**
* Initiate a remote wakeup of the host. The Device control register
* Remote Wakeup Signal bit is written if the PCD Remote wakeup enable
* flag is set.
*
*/
static ssize_t remote_wakeup_store(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifndef DWC_HOST_ONLY
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
uint32_t val = simple_strtoul(buf, NULL, 16);
if (val & 1)
dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
else
dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
#endif /* DWC_HOST_ONLY */
return count;
}
DEVICE_ATTR(remote_wakeup, S_IRUGO | S_IWUSR, remote_wakeup_show,
remote_wakeup_store);
/**
* Show the whether core is hibernated or not.
*/
static ssize_t rem_wakeup_pwrdn_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifndef DWC_HOST_ONLY
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
if (dwc_otg_get_core_state(otg_dev->core_if))
DWC_PRINTF("Core is in hibernation\n");
else
DWC_PRINTF("Core is not in hibernation\n");
#endif /* DWC_HOST_ONLY */
return 0;
}
/**
* Initiate a remote wakeup of the device to exit from hibernation.
*/
static ssize_t rem_wakeup_pwrdn_store(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifndef DWC_HOST_ONLY
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
dwc_otg_device_hibernation_restore(otg_dev->core_if, 1, 0);
#endif
return count;
}
DEVICE_ATTR(rem_wakeup_pwrdn, S_IRUGO | S_IWUSR, rem_wakeup_pwrdn_show,
rem_wakeup_pwrdn_store);
static ssize_t disconnect_us(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifndef DWC_HOST_ONLY
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
uint32_t val = simple_strtoul(buf, NULL, 16);
DWC_PRINTF("The Passed value is %04x\n", val);
dwc_otg_pcd_disconnect_us(otg_dev->pcd, 50);
#endif /* DWC_HOST_ONLY */
return count;
}
DEVICE_ATTR(disconnect_us, S_IWUSR, 0, disconnect_us);
/**
* Dump global registers and either host or device registers (depending on the
* current mode of the core).
*/
static ssize_t regdump_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
#ifdef CONFIG_KONA_USB_CONTROL
/* We want to be able to do this with and without
* USB-PMU-xceiver interface so use direct API
*/
bcm_hsotgctrl_en_clock(true);
dwc_otg_dump_global_registers(otg_dev->core_if);
if (dwc_otg_is_host_mode(otg_dev->core_if))
dwc_otg_dump_host_registers(otg_dev->core_if);
else
dwc_otg_dump_dev_registers(otg_dev->core_if);
bcm_hsotgctrl_en_clock(false);
#else
dwc_otg_dump_global_registers(otg_dev->core_if);
if (dwc_otg_is_host_mode(otg_dev->core_if))
dwc_otg_dump_host_registers(otg_dev->core_if);
else
dwc_otg_dump_dev_registers(otg_dev->core_if);
#endif
return sprintf(buf, "Register Dump\n");
}
DEVICE_ATTR(regdump, S_IRUGO | S_IWUSR, regdump_show, 0);
/**
* Dump global registers and either host or device registers (depending on the
* current mode of the core).
*/
static ssize_t spramdump_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
dwc_otg_dump_spram(otg_dev->core_if);
return sprintf(buf, "SPRAM Dump\n");
}
DEVICE_ATTR(spramdump, S_IRUGO | S_IWUSR, spramdump_show, 0);
/**
* Dump the current hcd state.
*/
static ssize_t hcddump_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifndef DWC_DEVICE_ONLY
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
dwc_otg_hcd_dump_state(otg_dev->hcd);
#endif /* DWC_DEVICE_ONLY */
return sprintf(buf, "HCD Dump\n");
}
DEVICE_ATTR(hcddump, S_IRUGO | S_IWUSR, hcddump_show, 0);
/**
* Dump the average frame remaining at SOF. This can be used to
* determine average interrupt latency. Frame remaining is also shown for
* start transfer and two additional sample points.
*/
static ssize_t hcd_frrem_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifndef DWC_DEVICE_ONLY
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
dwc_otg_hcd_dump_frrem(otg_dev->hcd);
#endif /* DWC_DEVICE_ONLY */
return sprintf(buf, "HCD Dump Frame Remaining\n");
}
DEVICE_ATTR(hcd_frrem, S_IRUGO | S_IWUSR, hcd_frrem_show, 0);
/**
* Displays the time required to read the GNPTXFSIZ register many times (the
* output shows the number of times the register is read).
*/
#define RW_REG_COUNT 10000000
#define MSEC_PER_JIFFIE (1000/HZ)
static ssize_t rd_reg_test_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
int i;
int time;
int start_jiffies;
pr_info("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
start_jiffies = jiffies;
for (i = 0; i < RW_REG_COUNT; i++)
dwc_otg_get_gnptxfsiz(otg_dev->core_if);
time = jiffies - start_jiffies;
return sprintf(buf,
"Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
}
DEVICE_ATTR(rd_reg_test, S_IRUGO | S_IWUSR, rd_reg_test_show, 0);
/**
* Displays the time required to write the GNPTXFSIZ register many times (the
* output shows the number of times the register is written).
*/
static ssize_t wr_reg_test_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
uint32_t reg_val;
int i;
int time;
int start_jiffies;
pr_info("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
reg_val = dwc_otg_get_gnptxfsiz(otg_dev->core_if);
start_jiffies = jiffies;
for (i = 0; i < RW_REG_COUNT; i++)
dwc_otg_set_gnptxfsiz(otg_dev->core_if, reg_val);
time = jiffies - start_jiffies;
return sprintf(buf,
"Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
}
DEVICE_ATTR(wr_reg_test, S_IRUGO | S_IWUSR, wr_reg_test_show, 0);
#ifdef CONFIG_USB_DWC_OTG_LPM
/**
* Show the lpm_response attribute.
*/
static ssize_t lpmresp_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if))
return sprintf(buf, "** LPM is DISABLED **\n");
if (!dwc_otg_is_device_mode(otg_dev->core_if))
return sprintf(buf, "** Current mode is not device mode\n");
return sprintf(buf, "lpm_response = %d\n",
dwc_otg_get_lpmresponse(otg_dev->core_if));
}
/**
* Store the lpm_response attribute.
*/
static ssize_t lpmresp_store(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
uint32_t val = simple_strtoul(buf, NULL, 16);
if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if))
return 0;
if (!dwc_otg_is_device_mode(otg_dev->core_if))
return 0;
dwc_otg_set_lpmresponse(otg_dev->core_if, val);
return count;
}
DEVICE_ATTR(lpm_response, S_IRUGO | S_IWUSR, lpmresp_show, lpmresp_store);
/**
* Show the sleep_status attribute.
*/
static ssize_t sleepstatus_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
return sprintf(buf, "Sleep Status = %d\n",
dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if));
}
/**
* Store the sleep_status attribure.
*/
static ssize_t sleepstatus_store(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
dwc_otg_core_if_t *core_if = otg_dev->core_if;
if (dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)) {
if (dwc_otg_is_host_mode(core_if)) {
DWC_PRINTF("Host initiated resume\n");
dwc_otg_set_prtresume(otg_dev->core_if, 1);
}
}
return count;
}
DEVICE_ATTR(sleep_status, S_IRUGO | S_IWUSR, sleepstatus_show,
sleepstatus_store);
#endif /* CONFIG_USB_DWC_OTG_LPM_ENABLE */
/**
* Show the value of Host mode Connection Timeout.
*/
static ssize_t h_conn_wait_tmout_show(struct device *_dev,
struct device_attribute *attr, char *buf)
{
#ifndef DWC_DEVICE_ONLY
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
return sprintf(buf, "Connection wait timeout in ms = %d\n",
otg_dev->hcd->conn_wait_timeout);
#else
return sprintf(buf, "Device Only Mode!\n");
#endif /* #ifndef DWC_DEVICE_ONLY */
}
/**
* Set the value of host mode connection timeout
*
*/
static ssize_t h_conn_wait_tmout_store(struct device *_dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
#ifndef DWC_DEVICE_ONLY
#ifdef LM_INTERFACE
struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
#elif defined(PCI_INTERFACE)
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
#else
struct platform_device *platform_dev =
container_of(_dev, struct platform_device, dev);
dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
#endif
otg_dev->hcd->conn_wait_timeout = simple_strtoul(buf, NULL, 10);
#endif
return count;
}
DEVICE_ATTR(h_conn_wait_tmout, S_IRUGO | S_IWUSR, h_conn_wait_tmout_show,
h_conn_wait_tmout_store);
/**@}*/
/**
* Create the device files
*/
void dwc_otg_attr_create(
#ifdef LM_INTERFACE
struct lm_device *dev
#elif defined(PCI_INTERFACE)
struct pci_dev *dev
#else
struct platform_device *dev
#endif
)
{
int error;
error = device_create_file(&dev->dev, &dev_attr_regoffset);
error = device_create_file(&dev->dev, &dev_attr_regvalue);
error = device_create_file(&dev->dev, &dev_attr_mode);
error = device_create_file(&dev->dev, &dev_attr_hnpcapable);
error = device_create_file(&dev->dev, &dev_attr_srpcapable);
error = device_create_file(&dev->dev, &dev_attr_hsic_connect);
error = device_create_file(&dev->dev, &dev_attr_inv_sel_hsic);
error = device_create_file(&dev->dev, &dev_attr_hnp);
error = device_create_file(&dev->dev, &dev_attr_srp);
error = device_create_file(&dev->dev, &dev_attr_buspower);
error = device_create_file(&dev->dev, &dev_attr_bussuspend);
error = device_create_file(&dev->dev, &dev_attr_busconnected);
error = device_create_file(&dev->dev, &dev_attr_gotgctl);
error = device_create_file(&dev->dev, &dev_attr_gusbcfg);
error = device_create_file(&dev->dev, &dev_attr_grxfsiz);
error = device_create_file(&dev->dev, &dev_attr_gnptxfsiz);
error = device_create_file(&dev->dev, &dev_attr_gpvndctl);
error = device_create_file(&dev->dev, &dev_attr_ggpio);
error = device_create_file(&dev->dev, &dev_attr_guid);
error = device_create_file(&dev->dev, &dev_attr_gsnpsid);
error = device_create_file(&dev->dev, &dev_attr_devspeed);
error = device_create_file(&dev->dev, &dev_attr_enumspeed);
error = device_create_file(&dev->dev, &dev_attr_hptxfsiz);
error = device_create_file(&dev->dev, &dev_attr_hprt0);
error = device_create_file(&dev->dev, &dev_attr_remote_wakeup);
error = device_create_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
error = device_create_file(&dev->dev, &dev_attr_disconnect_us);
error = device_create_file(&dev->dev, &dev_attr_regdump);
error = device_create_file(&dev->dev, &dev_attr_spramdump);
error = device_create_file(&dev->dev, &dev_attr_hcddump);
error = device_create_file(&dev->dev, &dev_attr_hcd_frrem);
error = device_create_file(&dev->dev, &dev_attr_rd_reg_test);
error = device_create_file(&dev->dev, &dev_attr_wr_reg_test);
#ifdef CONFIG_USB_DWC_OTG_LPM
error = device_create_file(&dev->dev, &dev_attr_lpm_response);
error = device_create_file(&dev->dev, &dev_attr_sleep_status);
#endif
error = device_create_file(&dev->dev, &dev_attr_h_conn_wait_tmout);
}
/**
* Remove the device files
*/
void dwc_otg_attr_remove(
#ifdef LM_INTERFACE
struct lm_device *dev
#elif defined(PCI_INTERFACE)
struct pci_dev *dev
#else
struct platform_device *dev
#endif
)
{
device_remove_file(&dev->dev, &dev_attr_regoffset);
device_remove_file(&dev->dev, &dev_attr_regvalue);
device_remove_file(&dev->dev, &dev_attr_mode);
device_remove_file(&dev->dev, &dev_attr_hnpcapable);
device_remove_file(&dev->dev, &dev_attr_srpcapable);
device_remove_file(&dev->dev, &dev_attr_hsic_connect);
device_remove_file(&dev->dev, &dev_attr_inv_sel_hsic);
device_remove_file(&dev->dev, &dev_attr_hnp);
device_remove_file(&dev->dev, &dev_attr_srp);
device_remove_file(&dev->dev, &dev_attr_buspower);
device_remove_file(&dev->dev, &dev_attr_bussuspend);
device_remove_file(&dev->dev, &dev_attr_busconnected);
device_remove_file(&dev->dev, &dev_attr_gotgctl);
device_remove_file(&dev->dev, &dev_attr_gusbcfg);
device_remove_file(&dev->dev, &dev_attr_grxfsiz);
device_remove_file(&dev->dev, &dev_attr_gnptxfsiz);
device_remove_file(&dev->dev, &dev_attr_gpvndctl);
device_remove_file(&dev->dev, &dev_attr_ggpio);
device_remove_file(&dev->dev, &dev_attr_guid);
device_remove_file(&dev->dev, &dev_attr_gsnpsid);
device_remove_file(&dev->dev, &dev_attr_devspeed);
device_remove_file(&dev->dev, &dev_attr_enumspeed);
device_remove_file(&dev->dev, &dev_attr_hptxfsiz);
device_remove_file(&dev->dev, &dev_attr_hprt0);
device_remove_file(&dev->dev, &dev_attr_remote_wakeup);
device_remove_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
device_remove_file(&dev->dev, &dev_attr_disconnect_us);
device_remove_file(&dev->dev, &dev_attr_regdump);
device_remove_file(&dev->dev, &dev_attr_spramdump);
device_remove_file(&dev->dev, &dev_attr_hcddump);
device_remove_file(&dev->dev, &dev_attr_hcd_frrem);
device_remove_file(&dev->dev, &dev_attr_rd_reg_test);
device_remove_file(&dev->dev, &dev_attr_wr_reg_test);
#ifdef CONFIG_USB_DWC_OTG_LPM
device_remove_file(&dev->dev, &dev_attr_lpm_response);
device_remove_file(&dev->dev, &dev_attr_sleep_status);
#endif
device_remove_file(&dev->dev, &dev_attr_h_conn_wait_tmout);
}
void w_conn_id_status_change(void *p)
{
dwc_otg_core_if_t *core_if = p;
uint32_t count = 0;
gotgctl_data_t gotgctl = {.d32 = 0 };
gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
/* B-Device connector (Device Mode) */
if (gotgctl.b.conidsts) {
/* Wait for switch to device mode. */
while (!dwc_otg_is_device_mode(core_if)) {
DWC_PRINTF("Waiting for Peripheral Mode, Mode=%s\n",
(dwc_otg_is_host_mode(core_if) ? "Host" :
"Peripheral"));
dwc_mdelay(100);
if (++count > 10000)
break;
}
DWC_ASSERT(++count < 10000,
"Connection id status change timed out");
core_if->op_state = B_PERIPHERAL;
#if defined(CONFIG_BATTERY_NXE2000)
otgid_power_control_by_dwc(0);
#elif defined(CONFIG_KP_AXP22)
axp_otg_power_control(0);
#endif
dwc_otg_set_prtpower(core_if, 0);
core_if->host_flag = 0;
dwc_otg_core_init(core_if);
dwc_otg_enable_global_interrupts(core_if);
cil_pcd_start(core_if);
} else {
/* A-Device connector (Host Mode) */
while (!dwc_otg_is_host_mode(core_if)) {
DWC_PRINTF("Waiting for Host Mode, Mode=%s\n",
(dwc_otg_is_host_mode(core_if) ? "Host" :
"Peripheral"));
dwc_mdelay(100);
if (++count > 10000)
break;
}
DWC_ASSERT(++count < 10000,
"Connection id status change timed out");
core_if->op_state = A_HOST;
/*
* Initialize the Core for Host mode.
*/
core_if->host_flag = 1;
dwc_otg_core_init(core_if);
dwc_otg_enable_global_interrupts(core_if);
cil_hcd_start(core_if);
}
}
/**
* This function handles the Connector ID Status Change Interrupt. It
* reads the OTG Interrupt Register (GOTCTL) to determine whether this
* is a Device to Host Mode transition or a Host Mode to Device
* Transition.
*
* This only occurs when the cable is connected/removed from the PHY
* connector.
*
* @param core_if Programming view of DWC_otg controller.
*/
int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t * core_if)
{
/*
* Need to disable SOF interrupt immediately. If switching from device
* to host, the PCD interrupt handler won't handle the interrupt if
* host mode is already set. The HCD interrupt handler won't get
* called if the HCD state is HALT. This means that the interrupt does
* not get handled and Linux complains loudly.
*/
gintmsk_data_t gintmsk = {.d32 = 0 };
gintsts_data_t gintsts = {.d32 = 0 };
gintmsk.b.sofintr = 1;
DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
DWC_DEBUGPL(DBG_CIL,
" ++Connector ID Status Change Interrupt++ (%s)\n",
(dwc_otg_is_host_mode(core_if) ? "Host" : "Device"));
DWC_SPINUNLOCK(core_if->lock);
/*
* Need to schedule a work, as there are possible DELAY function calls
* Release lock before scheduling workq as it holds spinlock during scheduling
*/
DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change,
core_if, "connection id status change");
DWC_SPINLOCK(core_if->lock);
/* Set flag and clear interrupt */
gintsts.b.conidstschng = 1;
DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/**
* This interrupt indicates that a device is initiating the Session
* Request Protocol to request the host to turn on bus power so a new
* session can begin. The handler responds by turning on bus power. If
* the DWC_otg controller is in low power mode, the handler brings the
* controller out of low power mode before turning on bus power.
*
* @param core_if Programming view of DWC_otg controller.
*/
int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * core_if)
{
gintsts_data_t gintsts;
#ifndef DWC_HOST_ONLY
DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
if (dwc_otg_is_device_mode(core_if)) {
DWC_PRINTF("SRP: Device mode\n");
} else {
hprt0_data_t hprt0;
DWC_PRINTF("SRP: Host mode\n");
/* Turn on the port power bit. */
hprt0.d32 = dwc_otg_read_hprt0(core_if);
hprt0.b.prtpwr = 1;
DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
/* Start the Connection timer. So a message can be displayed
* if connect does not occur within 10 seconds. */
cil_hcd_session_start(core_if);
}
#endif
/* Clear interrupt */
gintsts.d32 = 0;
gintsts.b.sessreqintr = 1;
DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
void w_wakeup_detected(void *p)
{
dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) p;
/*
* Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
* so that OPT tests pass with all PHYs).
*/
hprt0_data_t hprt0 = {.d32 = 0 };
#if 0
pcgcctl_data_t pcgcctl = {.d32 = 0 };
/* Restart the Phy Clock */
pcgcctl.b.stoppclk = 1;
DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
dwc_udelay(10);
#endif //0
hprt0.d32 = dwc_otg_read_hprt0(core_if);
DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32);
// dwc_mdelay(70);
hprt0.b.prtres = 0; /* Resume */
DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n",
DWC_READ_REG32(core_if->host_if->hprt0));
cil_hcd_resume(core_if);
/** Change to L0 state*/
core_if->lx_state = DWC_OTG_L0;
}
/**
* This interrupt indicates that the DWC_otg controller has detected a
* resume or remote wakeup sequence. If the DWC_otg controller is in
* low power mode, the handler must brings the controller out of low
* power mode. The controller automatically begins resume
* signaling. The handler schedules a time to stop resume signaling.
*/
int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
{
gintsts_data_t gintsts;
DWC_DEBUGPL(DBG_ANY,
"++Resume and Remote Wakeup Detected Interrupt++\n");
DWC_PRINTF("%s lxstate = %d\n", __func__, core_if->lx_state);
if (dwc_otg_is_device_mode(core_if)) {
dctl_data_t dctl = {.d32 = 0 };
DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
dsts));
if (core_if->lx_state == DWC_OTG_L2) {
#ifdef PARTIAL_POWER_DOWN
if (core_if->hwcfg4.b.power_optimiz) {
pcgcctl_data_t power = {.d32 = 0 };
power.d32 = DWC_READ_REG32(core_if->pcgcctl);
DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n",
power.d32);
power.b.stoppclk = 0;
DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
power.b.pwrclmp = 0;
DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
power.b.rstpdwnmodule = 0;
DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
}
#endif
/* Clear the Remote Wakeup Signaling */
dctl.b.rmtwkupsig = 1;
DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
dctl, dctl.d32, 0);
DWC_SPINUNLOCK(core_if->lock);
if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
}
DWC_SPINLOCK(core_if->lock);
} else {
glpmcfg_data_t lpmcfg;
lpmcfg.d32 =
DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
lpmcfg.b.hird_thres &= (~(1 << 4));
DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
lpmcfg.d32);
}
/** Change to L0 state*/
core_if->lx_state = DWC_OTG_L0;
} else {
if (core_if->lx_state != DWC_OTG_L1) {
pcgcctl_data_t pcgcctl = {.d32 = 0 };
/* Restart the Phy Clock */
pcgcctl.b.stoppclk = 1;
DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
DWC_TIMER_SCHEDULE(core_if->wkp_timer, 71);
} else {
/** Change to L0 state*/
core_if->lx_state = DWC_OTG_L0;
}
}
int dwc_dh_derive_keys(uint8_t nd, uint8_t *pkh, uint8_t *pkd,
uint8_t *exp, int is_host,
char *dd, uint8_t *ck, uint8_t *kdk)
{
int retval;
uint8_t mv[784];
uint8_t sha_result[32];
uint8_t dhkey[384];
uint8_t shared_secret[384];
char *message;
uint32_t vd;
uint8_t *pk;
if (is_host) {
pk = pkd;
}
else {
pk = pkh;
}
if ((retval = dwc_dh_modpow(pk, 384,
exp, 32,
dh_p, 384, shared_secret))) {
return retval;
}
dh_dump("Shared Secret", shared_secret, 384);
DWC_SHA256(shared_secret, 384, dhkey);
dh_dump("DHKEY", dhkey, 384);
DWC_MEMCPY(&mv[0], pkd, 384);
DWC_MEMCPY(&mv[384], pkh, 384);
DWC_MEMCPY(&mv[768], "displayed digest", 16);
dh_dump("MV", mv, 784);
DWC_SHA256(mv, 784, sha_result);
dh_dump("SHA-256(MV)", sha_result, 32);
dh_dump("First 32-bits of SHA-256(MV)", sha_result, 4);
dh_swap_bytes(sha_result, &vd, 4);
#ifdef DEBUG
DWC_PRINTF("Vd (decimal) = %d\n", vd);
#endif
switch (nd) {
case 2:
vd = vd % 100;
DWC_SPRINTF(dd, "%02d", vd);
break;
case 3:
vd = vd % 1000;
DWC_SPRINTF(dd, "%03d", vd);
break;
case 4:
vd = vd % 10000;
DWC_SPRINTF(dd, "%04d", vd);
break;
}
#ifdef DEBUG
DWC_PRINTF("Display Digits: %s\n", dd);
#endif
message = "connection key";
DWC_HMAC_SHA256(message, DWC_STRLEN(message), dhkey, 32, sha_result);
dh_dump("HMAC(SHA-256, DHKey, connection key)", sha_result, 32);
DWC_MEMCPY(ck, sha_result, 16);
message = "key derivation key";
DWC_HMAC_SHA256(message, DWC_STRLEN(message), dhkey, 32, sha_result);
dh_dump("HMAC(SHA-256, DHKey, key derivation key)", sha_result, 32);
DWC_MEMCPY(kdk, sha_result, 32);
return 0;
}
/**
* Sets the final status of an URB and returns it to the device driver. Any
* required cleanup of the URB is performed.
*/
static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle,
dwc_otg_hcd_urb_t * dwc_otg_urb, uint32_t status)
{
struct urb *urb = (struct urb *)urb_handle;
#ifdef DEBUG
if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
DWC_PRINTF("%s: urb %p, device %d, ep %d %s, status=%d\n",
__func__, urb, usb_pipedevice(urb->pipe),
usb_pipeendpoint(urb->pipe),
usb_pipein(urb->pipe) ? "IN" : "OUT", status);
if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
int i;
for (i = 0; i < urb->number_of_packets; i++) {
DWC_PRINTF(" ISO Desc %d status: %d\n",
i, urb->iso_frame_desc[i].status);
}
}
}
#endif
urb->actual_length = dwc_otg_hcd_urb_get_actual_length(dwc_otg_urb);
/* Convert status value. */
switch (status) {
case -DWC_E_PROTOCOL:
status = -EPROTO;
break;
case -DWC_E_IN_PROGRESS:
status = -EINPROGRESS;
break;
case -DWC_E_PIPE:
status = -EPIPE;
break;
case -DWC_E_IO:
status = -EIO;
break;
case -DWC_E_TIMEOUT:
status = -ETIMEDOUT;
break;
default:
if (status) {
/* alan.K
* DWC_OTG IP don't know this status, so assumed to be a DWC_E_PROTOCOL.
*/
DWC_WARN("Unknown urb status %d, but assumed to be an EPROTO\n", status);
status = -EPROTO;
}
}
if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
int i;
urb->error_count = dwc_otg_hcd_urb_get_error_count(dwc_otg_urb);
for (i = 0; i < urb->number_of_packets; ++i) {
urb->iso_frame_desc[i].actual_length =
dwc_otg_hcd_urb_get_iso_desc_actual_length
(dwc_otg_urb, i);
urb->iso_frame_desc[i].status =
dwc_otg_hcd_urb_get_iso_desc_actual_length
(dwc_otg_urb, i);
}
}
urb->status = status;
urb->hcpriv = NULL;
if (!status) {
if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
(urb->actual_length < urb->transfer_buffer_length)) {
urb->status = -EREMOTEIO;
}
}
if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) ||
(usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
if (ep) {
free_bus_bandwidth(dwc_otg_hcd_to_hcd(hcd),
dwc_otg_hcd_get_ep_bandwidth(hcd, ep->hcpriv),
urb);
}
}
dwc_free(dwc_otg_urb);
usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, status);
return 0;
}
