boolean CInterruptSystem::Initialize (void)
{
TExceptionTable *pTable = (TExceptionTable *) ARM_EXCEPTION_TABLE_BASE;
pTable->IRQ = ARM_OPCODE_BRANCH (ARM_DISTANCE (pTable->IRQ, IRQStub));
CleanDataCache ();
DataSyncBarrier ();
InvalidateInstructionCache ();
FlushBranchTargetCache ();
DataSyncBarrier ();
InstructionSyncBarrier ();
#ifndef USE_RPI_STUB_AT
DataMemBarrier ();
write32 (ARM_IC_FIQ_CONTROL, 0);
write32 (ARM_IC_DISABLE_IRQS_1, (u32) -1);
write32 (ARM_IC_DISABLE_IRQS_2, (u32) -1);
write32 (ARM_IC_DISABLE_BASIC_IRQS, (u32) -1);
DataMemBarrier ();
#endif
EnableInterrupts ();
return TRUE;
}
boolean CBcmPropertyTags::GetTag (u32 nTagId, void *pTag, unsigned nTagSize, unsigned nRequestParmSize)
{
assert (pTag != 0);
assert (nTagSize >= sizeof (TPropertyTagSimple));
unsigned nBufferSize = sizeof (TPropertyBuffer) + nTagSize + sizeof (u32);
assert ((nBufferSize & 3) == 0);
// cannot use "new" here because this is used before mem_init() is called
u8 Buffer[nBufferSize + 15];
TPropertyBuffer *pBuffer = (TPropertyBuffer *) (((u32) Buffer + 15) & ~15);
pBuffer->nBufferSize = nBufferSize;
pBuffer->nCode = CODE_REQUEST;
memcpy (pBuffer->Tags, pTag, nTagSize);
TPropertyTag *pHeader = (TPropertyTag *) pBuffer->Tags;
pHeader->nTagId = nTagId;
pHeader->nValueBufSize = nTagSize - sizeof (TPropertyTag);
pHeader->nValueLength = nRequestParmSize & ~VALUE_LENGTH_RESPONSE;
u32 *pEndTag = (u32 *) (pBuffer->Tags + nTagSize);
*pEndTag = PROPTAG_END;
CleanDataCache ();
DataSyncBarrier ();
u32 nBufferAddress = GPU_MEM_BASE + (u32) pBuffer;
if (m_MailBox.WriteRead (nBufferAddress) != nBufferAddress)
{
return FALSE;
}
InvalidateDataCache ();
DataSyncBarrier ();
if (pBuffer->nCode != CODE_RESPONSE_SUCCESS)
{
return FALSE;
}
if (!(pHeader->nValueLength & VALUE_LENGTH_RESPONSE))
{
return FALSE;
}
pHeader->nValueLength &= ~VALUE_LENGTH_RESPONSE;
if (pHeader->nValueLength == 0)
{
return FALSE;
}
memcpy (pTag, pBuffer->Tags, nTagSize);
return TRUE;
}
CTranslationTable::CTranslationTable (u64 nMemSize)
: m_nMemSize (nMemSize),
m_pTable (0)
{
m_pTable = (TARMV8MMU_LEVEL2_DESCRIPTOR *) palloc ();
assert (m_pTable != 0);
memset (m_pTable, 0, PAGE_SIZE);
for (unsigned nEntry = 0; nEntry < 3; nEntry++) // 3 entries a 512MB
{
u64 nBaseAddress = (u64) nEntry * ARMV8MMU_TABLE_ENTRIES * ARMV8MMU_LEVEL3_PAGE_SIZE;
TARMV8MMU_LEVEL3_DESCRIPTOR *pTable = CreateLevel3Table (nBaseAddress);
assert (pTable != 0);
TARMV8MMU_LEVEL2_TABLE_DESCRIPTOR *pDesc = &m_pTable[nEntry].Table;
pDesc->Value11 = 3;
pDesc->Ignored1 = 0;
pDesc->TableAddress = ARMV8MMUL2TABLEADDR ((u64) pTable);
pDesc->Reserved0 = 0;
pDesc->Ignored2 = 0;
pDesc->PXNTable = 0;
pDesc->UXNTable = 0;
pDesc->APTable = AP_TABLE_ALL_ACCESS;
pDesc->NSTable = 0;
}
DataSyncBarrier ();
}
void PageTable2 (TPageTable *This, uint32 MemSize)
{
This->TableAllocated = true;
This->Table = (TARMV6MMU_LEVEL1_SECTION_DESCRIPTOR *) PageAlloc();
for (unsigned EntryIndex = 0; EntryIndex < SDRAM_SIZE_MBYTE; EntryIndex++)
{
uint32 BaseAddress = MEGABYTE * EntryIndex;
TARMV6MMU_LEVEL1_SECTION_DESCRIPTOR* Entry = &This->Table[EntryIndex];
Entry->Value10 = 2;
Entry->BBit = 1;
Entry->CBit = 1;
Entry->XNBit = 0;
Entry->Domain = 0;
Entry->IMPBit = 0;
Entry->AP = AP_SYSTEM_ACCESS;
Entry->TEX = 0;
Entry->APXBit = APX_RW_ACCESS;
Entry->SBit = 0;
Entry->NGBit = 0;
Entry->Value0 = 0;
Entry->SBZ = 0;
Entry->Base = ARMV6MMUL1SECTIONBASE(BaseAddress);
}
CleanDataCache ();
DataSyncBarrier ();
}
void PageTable(TPageTable* This)
{
This->TableAllocated = false;
This->Table = (TARMV6MMU_LEVEL1_SECTION_DESCRIPTOR*) MEM_PAGE_TABLE1;
for (unsigned EntryIndex = 0; EntryIndex < 4096; EntryIndex++)
{
uint32 nBaseAddress = MEGABYTE * EntryIndex;
TARMV6MMU_LEVEL1_SECTION_DESCRIPTOR* Entry = &This->Table[EntryIndex];
Entry->Value10 = 2;
Entry->BBit = 1;
Entry->CBit = 0;
Entry->XNBit = 0;
Entry->Domain = 0;
Entry->IMPBit = 0;
Entry->AP = AP_SYSTEM_ACCESS;
Entry->TEX = 0;
Entry->APXBit = APX_RW_ACCESS;
Entry->SBit = 0;
Entry->NGBit = 0;
Entry->Value0 = 0;
Entry->SBZ = 0;
Entry->Base = ARMV6MMUL1SECTIONBASE(nBaseAddress);
}
CleanDataCache ();
DataSyncBarrier ();
}
void PageTable2 (TPageTable *pThis, u32 nMemSize)
{
assert (pThis != 0);
pThis->m_bTableAllocated = TRUE;
pThis->m_pTable = (TARMV6MMU_LEVEL1_SECTION_DESCRIPTOR *) palloc ();
assert (pThis->m_pTable != 0);
assert (((u32) pThis->m_pTable & 0xFFF) == 0);
for (unsigned nEntry = 0; nEntry < SDRAM_SIZE_MBYTE; nEntry++)
{
u32 nBaseAddress = MEGABYTE * nEntry;
TARMV6MMU_LEVEL1_SECTION_DESCRIPTOR *pEntry = &pThis->m_pTable[nEntry];
// outer and inner write back, no write allocate
pEntry->Value10 = 2;
pEntry->BBit = 1;
pEntry->CBit = 1;
pEntry->XNBit = 0;
pEntry->Domain = 0;
pEntry->IMPBit = 0;
pEntry->AP = AP_SYSTEM_ACCESS;
pEntry->TEX = 0;
pEntry->APXBit = APX_RW_ACCESS;
pEntry->SBit = 0;
pEntry->NGBit = 0;
pEntry->Value0 = 0;
pEntry->SBZ = 0;
pEntry->Base = ARMV6MMUL1SECTIONBASE (nBaseAddress);
extern u8 _etext;
if (nBaseAddress >= (u32) &_etext)
{
pEntry->XNBit = 1;
if (nBaseAddress >= nMemSize)
{
// shared device
pEntry->BBit = 1;
pEntry->CBit = 0;
pEntry->TEX = 0;
pEntry->SBit = 1;
}
}
}
CleanDataCache ();
DataSyncBarrier ();
}
void PageTable (TPageTable *pThis)
{
assert (pThis != 0);
pThis->m_bTableAllocated = FALSE;
pThis->m_pTable = (TARMV6MMU_LEVEL1_SECTION_DESCRIPTOR *) MEM_PAGE_TABLE1;
assert (((u32) pThis->m_pTable & 0x3FFF) == 0);
for (unsigned nEntry = 0; nEntry < 4096; nEntry++)
{
u32 nBaseAddress = MEGABYTE * nEntry;
TARMV6MMU_LEVEL1_SECTION_DESCRIPTOR *pEntry = &pThis->m_pTable[nEntry];
// shared device
pEntry->Value10 = 2;
pEntry->BBit = 1;
pEntry->CBit = 0;
pEntry->XNBit = 0;
pEntry->Domain = 0;
pEntry->IMPBit = 0;
pEntry->AP = AP_SYSTEM_ACCESS;
pEntry->TEX = 0;
pEntry->APXBit = APX_RW_ACCESS;
pEntry->SBit = 1;
pEntry->NGBit = 0;
pEntry->Value0 = 0;
pEntry->SBZ = 0;
pEntry->Base = ARMV6MMUL1SECTIONBASE (nBaseAddress);
if (nEntry >= SDRAM_SIZE_MBYTE)
{
pEntry->XNBit = 1;
}
}
CleanDataCache ();
DataSyncBarrier ();
}
boolean CBcmPropertyTags::GetTags (void *pTags, unsigned nTagsSize)
{
assert (pTags != 0);
assert (nTagsSize >= sizeof (TPropertyTagSimple));
unsigned nBufferSize = sizeof (TPropertyBuffer) + nTagsSize + sizeof (u32);
assert ((nBufferSize & 3) == 0);
TPropertyBuffer *pBuffer =
(TPropertyBuffer *) CMemorySystem::GetCoherentPage (COHERENT_SLOT_PROP_MAILBOX);
pBuffer->nBufferSize = nBufferSize;
pBuffer->nCode = CODE_REQUEST;
memcpy (pBuffer->Tags, pTags, nTagsSize);
u32 *pEndTag = (u32 *) (pBuffer->Tags + nTagsSize);
*pEndTag = PROPTAG_END;
DataSyncBarrier ();
u32 nBufferAddress = GPU_MEM_BASE + (u32) pBuffer;
if (m_MailBox.WriteRead (nBufferAddress) != nBufferAddress)
{
return FALSE;
}
DataMemBarrier ();
if (pBuffer->nCode != CODE_RESPONSE_SUCCESS)
{
return FALSE;
}
memcpy (pTags, pBuffer->Tags, nTagsSize);
return TRUE;
}
