void DoCode( mad_disasm_data *dd, int big )
{
DisDecodeInit( &DH, &dd->ins );
dd->addr = DbgAddr;
dd->ins.flags.u.x86 = DIF_X86_NONE;
if( big ) {
dd->ins.flags.u.x86 = DIF_X86_USE32_FLAGS;
}
DisDecode( &DH, dd, &dd->ins );
}
static void dumpCodeBuff( void (*output)( char ),
code_buff *buff )
{
dis_handle handle;
dis_dec_ins ins;
char name[ MAX_INS_NAME ];
char ops[ MAX_OBJ_NAME + 24 ];
DisInit( buff->cpu, &handle );
while( buff->offset < buff->length ){
DisDecodeInit( &handle, &ins );
if( buff->cpu == DISCPU_x86 ) {
ins.flags |= DIF_X86_USE32_FLAGS;
}
DisDecode( &handle, buff, &ins );
DisFormat( &handle, buff, &ins, DFF_AXP_SYMBOLIC_REG|DFF_PSEUDO, &name, &ops );
myPrintf( output, "\t%4.4x:", buff->offset );
dumpOpcodes( output, buff->start+buff->offset, ins.size );
myPrintf( output, "\t%s\t%s\n", name, ops );
buff->offset += ins.size;
}
DisFini( &handle );
}
return_val DoPass1( orl_sec_handle shnd, unsigned_8 *contents, orl_sec_size size,
ref_list sec_ref_list, scantab_ptr stl )
// perform pass 1 on one section
{
orl_sec_offset loop;
dis_dec_ins decoded;
dis_value value;
dis_return dr;
unnamed_label_return_struct rs;
return_val error;
unsigned i;
ref_entry r_entry;
dis_inst_flags flags;
orl_sec_offset op_pos;
int is_intel;
int adjusted;
sa_disasm_struct sds;
sds.data = contents;
sds.last = size - 1;
if( sec_ref_list != NULL ) {
r_entry = sec_ref_list->first;
} else {
r_entry = NULL;
}
flags.u.all = DIF_NONE;
if( GetMachineType() == ORL_MACHINE_TYPE_I386 ) {
if( ( GetFormat() != ORL_OMF ) ||
( ORLSecGetFlags( shnd ) & ORL_SEC_FLAG_USE_32 ) ) {
flags.u.x86 = DIF_X86_USE32_FLAGS;
}
is_intel = 1;
} else {
is_intel = IsIntelx86();
}
for( loop = 0; loop < size; loop += decoded.size ) {
// skip data in code segment
while( stl && ( loop > stl->end ) ) {
stl = stl->next;
}
if( stl && ( loop >= stl->start ) ) {
decoded.size = 0;
if( is_intel ) {
r_entry = DoPass1Relocs( contents, r_entry, loop, stl->end );
}
loop = stl->end;
stl = stl->next;
continue;
}
// data may not be listed in scan table, but a fixup at this offset will
// give it away
while( r_entry && ( ( r_entry->offset < loop ) || SkipRef(r_entry) ) ) {
r_entry = r_entry->next;
}
if( r_entry && ( r_entry->offset == loop ) ) {
if( is_intel || IsDataReloc( r_entry ) ) {
// we just skip the data
op_pos = loop;
decoded.size = 0;
loop += RelocSize( r_entry );
r_entry = DoPass1Relocs( contents, r_entry, op_pos, loop );
continue;
}
}
DisDecodeInit( &DHnd, &decoded );
decoded.flags.u.all |= flags.u.all;
sds.offs = loop;
dr = DisDecode( &DHnd, &sds, &decoded );
// if an invalid instruction was found, there is nothing we can do.
if( dr != DR_OK )
return( RC_ERROR );
for( i = 0; i < decoded.num_ops; ++i ) {
adjusted = 0;
op_pos = loop + decoded.op[i].op_position;
switch( decoded.op[i].type & DO_MASK ) {
case DO_IMMED:
if( !is_intel )
break;
/* fall through */
case DO_RELATIVE:
case DO_MEMORY_REL:
if( ( decoded.op[i].type & DO_MASK ) != DO_IMMED ) {
decoded.op[i].value += loop;
adjusted = 1;
}
/* fall through */
case DO_ABSOLUTE:
case DO_MEMORY_ABS:
// Check for reloc at this location
while( r_entry && r_entry->offset < op_pos ) {
r_entry = r_entry->next;
}
if( r_entry && ( r_entry->offset == op_pos ) ) {
if( is_intel && r_entry->label->shnd
&& ( r_entry->type != ORL_RELOC_TYPE_SEGMENT )
&& ( r_entry->label->type == LTYP_SECTION ) ) {
/* For section offsets under intel we MUST generate a
* local label because the offset might change when the
* code is re-assembled
*/
if( r_entry->addend ) {
r_entry->no_val = 0;
CreateUnnamedLabel( r_entry->label->shnd,
HandleAddend( r_entry ), &rs );
} else {
r_entry->no_val = 1;
if( adjusted && isSelfReloc( r_entry ) &&
( r_entry->label->type == LTYP_SECTION ) ) {
/* This is a kludgy reloc done under OMF
*/
decoded.op[i].value -= loop;
decoded.op[i].value -= decoded.size;
switch( RelocSize( r_entry ) ) {
case( 2 ):
decoded.op[i].value =
(uint_16)(decoded.op[i].value);
case( 1 ):
decoded.op[i].value =
(uint_8)(decoded.op[i].value);
}
}
value = decoded.op[i].value;
if( value < 0 || value > ORLSecGetSize( r_entry->label->shnd ) ) {
// can't fold it into the label position - BBB Oct 28, 1996
value = 0;
r_entry->no_val = 0;
}
CreateUnnamedLabel( r_entry->label->shnd, value, &rs );
}
if( rs.error != RC_OKAY )
return( rs.error );
r_entry->label = rs.entry;
} else {
// fixme: got to handle other types of relocs here
}
} else if( ( decoded.op[i].type & DO_MASK ) != DO_IMMED ) {
if( decoded.op[i].base == DR_NONE &&
decoded.op[i].index == DR_NONE ) {
switch( decoded.op[i].type & DO_MASK ) {
case DO_MEMORY_REL:
case DO_MEMORY_ABS:
// use decoded instruction size for absolute memory on amd64.
// the cpu will reference rip _after_ the instruction is
// completely fetched and decoded.
// relocations in pass2 are not applied because they break
// relative memory references if no relocation is present!
if( GetMachineType() == ORL_MACHINE_TYPE_AMD64 ) {
decoded.op[i].value += decoded.size;
// I don't know if this is neccessary, but it will generate
// labels for memory references if no symbol is present
// (ex: executable file)
CreateUnnamedLabel( shnd, decoded.op[i].value, &rs );
if( rs.error != RC_OKAY )
return( rs.error );
error = CreateUnnamedLabelRef( shnd, rs.entry, op_pos );
} else {
// create an LTYP_ABSOLUTE label
CreateAbsoluteLabel( shnd, decoded.op[i].value, &rs );
if( rs.error != RC_OKAY )
return( rs.error );
error = CreateAbsoluteLabelRef( shnd, rs.entry, op_pos );
}
break;
default:
// create an LTYP_UNNAMED label
CreateUnnamedLabel( shnd, decoded.op[i].value, &rs );
if( rs.error != RC_OKAY )
return( rs.error );
error = CreateUnnamedLabelRef( shnd, rs.entry, op_pos );
break;
}
if( error != RC_OKAY ) {
return( error );
}
}
}
break;
}
}
}
return( RC_OKAY );
}
num_errors DoPass2( section_ptr sec, unsigned_8 *contents, orl_sec_size size,
label_list sec_label_list, ref_list sec_ref_list )
// perform pass 2 on one section
{
struct pass2 data;
label_entry l_entry;
dis_dec_ins decoded;
char name[ MAX_INS_NAME ];
char ops[ MAX_OBJ_NAME + 24 ]; // at most 1 label/relocation per instruction, plus room for registers, brackets and other crap
dis_inst_flags flags;
scantab_ptr st;
int is_intel;
sa_disasm_struct sds;
char *FPU_fixup;
int pos_tabs;
bool is32bit;
routineBase = 0;
st = sec->scan;
data.size = size;
sds.data = contents;
sds.last = size - 1;
l_entry = NULL;
if( sec_label_list != NULL ) {
l_entry = sec_label_list->first;
}
if( sec_ref_list != NULL ) {
data.r_entry = sec_ref_list->first;
} else {
data.r_entry = NULL;
}
data.disassembly_errors = 0;
if( source_mix ) {
GetSourceFile( sec );
}
PrintHeader( sec );
if( size && sec_label_list )
PrintAssumeHeader( sec );
flags.u.all = DIF_NONE;
if( GetMachineType() == ORL_MACHINE_TYPE_I386 ) {
if( ( GetFormat() != ORL_OMF ) ||
( ORLSecGetFlags( sec->shnd ) & ORL_SEC_FLAG_USE_32 ) ) {
flags.u.x86 = DIF_X86_USE32_FLAGS;
}
is_intel = 1;
} else {
is_intel = IsIntelx86();
}
is32bit = ( size >= 0x10000 );
for( data.loop = 0; data.loop < size; data.loop += decoded.size ) {
// process data in code segment
while( st && ( data.loop > st->end ) ) {
st = st->next;
}
if( st && ( data.loop >= st->start ) ) {
decoded.size = 0;
processDataInCode( sec, contents, &data, st->end - data.loop, &l_entry );
st = st->next;
continue;
}
// data may not be listed in scan table, but a fixup at this offset will
// give it away
while( data.r_entry && ( data.r_entry->offset < data.loop ) ) {
data.r_entry = data.r_entry->next;
}
FPU_fixup = processFpuEmulatorFixup( &data.r_entry, data.loop );
if( data.r_entry && ( data.r_entry->offset == data.loop ) ) {
if( is_intel || IsDataReloc( data.r_entry ) ) {
// we just skip the data
decoded.size = 0;
processDataInCode( sec, contents, &data, RelocSize( data.r_entry ), &l_entry );
continue;
}
}
if( source_mix ) {
MixSource( data.loop );
}
DisDecodeInit( &DHnd, &decoded );
decoded.flags.u.all |= flags.u.all;
sds.offs = data.loop;
DisDecode( &DHnd, &sds, &decoded );
if( sec_label_list ) {
l_entry = handleLabels( sec->name, data.loop, data.loop + decoded.size, l_entry, size );
if( ( l_entry != NULL )
&& ( l_entry->offset > data.loop )
&& ( l_entry->offset < data.loop + decoded.size ) ) {
/*
If we have a label planted in the middle of this
instruction (see inline memchr for example), put
out a couple of data bytes, and then restart decode
and label process from offset of actual label.
*/
decoded.size = 0;
processDataInCode( sec, contents, &data, l_entry->offset - data.loop, &l_entry );
continue;
}
}
DisFormat( &DHnd, &data, &decoded, DFormat, name, sizeof( name ), ops, sizeof( ops ) );
if( FPU_fixup != NULL ) {
if( !(DFormat & DFF_ASM) ) {
BufferAlignToTab( PREFIX_SIZE_TABS );
}
BufferStore( "\t%sFPU fixup %s\n", CommentString, FPU_fixup );
}
if( !(DFormat & DFF_ASM) ) {
unsigned_64 *tmp_64;
unsigned_32 *tmp_32;
unsigned_16 *tmp_16;
tmp_64 = (unsigned_64 *)(contents + data.loop);
tmp_32 = (unsigned_32 *)(contents + data.loop);
tmp_16 = (unsigned_16 *)(contents + data.loop);
if( DHnd.need_bswap ) {
switch( DisInsSizeInc( &DHnd ) ) {
//case 8: SWAP_64( *tmp_64 );
// break;
case 4: SWAP_32( *tmp_32 );
break;
case 2: SWAP_16( *tmp_16 );
break;
default:
break;
}
}
PrintLinePrefixAddress( data.loop, is32bit );
PrintLinePrefixData( contents, data.loop, size, DisInsSizeInc( &DHnd ), decoded.size );
BufferAlignToTab( PREFIX_SIZE_TABS );
}
BufferStore( "\t%s", name );
if( *ops != '\0' ) {
pos_tabs = ( DisInsNameMax( &DHnd ) + TAB_WIDTH ) / TAB_WIDTH + 1;
if( !(DFormat & DFF_ASM) ) {
pos_tabs += PREFIX_SIZE_TABS;
}
BufferAlignToTab( pos_tabs );
BufferConcat( ops );
}
BufferConcatNL();
BufferPrint();
}
if( sec_label_list ) {
l_entry = handleLabels( sec->name, size, (orl_sec_offset)-1, l_entry, size );
}
if( !(DFormat & DFF_ASM) ) {
routineSize = data.loop - routineBase;
BufferConcatNL();
BufferMsg( ROUTINE_SIZE );
BufferStore(" %d ", routineSize );
BufferMsg( BYTES );
BufferConcat(", ");
BufferMsg( ROUTINE_BASE );
BufferStore(" %s + %04X\n\n", sec->name, routineBase );
BufferPrint();
}
if( source_mix ) {
EndSourceMix();
}
PrintTail( sec );
return( data.disassembly_errors );
}
